A compact cost-effective Narrowband Internet-of-Things (NB-IoT) System-in-Package (SiP) in mass production is implemented in 55nm CMOS and Integrated Passive Device (IPD) process. The RF front-end components, i.e., inductors and capacitors, are integrated into an IPD die to reduce the Bill of Material (BOM) cost. Notably, the design eliminated the necessity of the antenna switches (ANTSW). On the IPD die, a diplexer is employed to separate the low-band (LB) and high-band (HB) paths, while in each band, the transmitter (TX) and the receiver (RX) share a common RF low pass filter through a co-matching network. To ensure robust performance, CMOS switches are placed at the PA’s drain and the LNA’s input, protecting the LNA core devices from breaking down and tuning essential impedance matching for both TX and RX. The built-in self-calibration scheme enables the chip to calibrate its TX/RX gain autonomously and flexibly, eliminating the use of external equipment therefore reducing the cost at the module production line. The NB-IoT SoC is integrated with the IPD die in a$7\times 7$QFN package. The system operates across the NB-IoT bands from 699MHz to 2200MHz (the CMOS chip supports 450MHz to 2200MHz), with transmitter’s Psatover +26dBm and achieving the HD2/HD3 below −36dBm when transmitting at +23dBm. The self-calibration scheme improves TX LO leakage and image by more than 15dB and ensures TX/RX gain accuracy within +/−0.5dB across the band and gain states.

Abstract Museum web interfaces continue to be important in how users search for information and navigate through digital cultural heritage resources. A generous interface was deemed appropriate for displaying large amounts of digital cultural heritage. However, more example verification is required in this field of study. This study compared the traditional interface and the generous interface of the Liaoning Provincial Museum to investigate the role of a generous interface for cultural heritage collections. Forty second‐year design graduate students were randomly assigned to one of two interface groups: traditional interface or generous interface. Four variables were measured to compare the differences between the two interfaces for the participants. In addition, two parameters, holding time and average retrieval time, are recorded and used to evaluate and compare the impact of the two interfaces on user behavior. The generous interface, according to the findings, is more effective than the traditional interface in increasing participants' engagement with cultural heritage and is perceived to be more aesthetically pleasing. In addition, the generous interface has been proven to be more suitable for casual leisure users to explore cultural heritage information. This research provides the basis and reference for developing the web interface of cultural heritage collections.

Abstract This study explores a game model that uses scaffolding to learn about cultural heritage based on adventure games. A case study using traditional Chinese murals tested the effectiveness of serious games in improving learning performance and knowledge acquisition. This study observed and evaluated the learning outcomes of 64 students by using serious game learning compared to traditional video learning in an experimental setting. Changes in knowledge acquisition, intrinsic motivation, cognitive load (extrinsic load vs. germane load), and engagement were collected through a series of tests and scales. Experimental results show that digital adventure games have better learning performance and knowledge retention effects, higher intrinsic motivation, germane load, and engagement than traditional video learning. The reasons affecting academic performance were analyzed from the data, and it was found that intrinsic motivation and germane cognitive load positively affected game performance, and external cognitive load hurt game performance. This study provides experience on the design of serious games in cultural heritage learning.

This paper presents a 2.85-mm2 0.4-6 GHz RF transceiver in 40-nm CMOS for low-cost and low-power IoT micro-hub applications. A single-path receiver (RX), an all-digital phase-locked loop (ADPLL), and a digital transmitter (DTX) (including a digital power amplifier, DPA) are integrated. In the RX, to reduce the chip area and power consumption, an inductor-less capacitive-feedforward wideband LNA and a Gm-C filter-based dc offset cancellation (Gm-C-DCOC) technique are proposed. The RX achieves a noise figure (NF) of 1.3-4.9 dB over 0.4-6 GHz while consuming 31 mW. The measured average IIP3, in-band P1dB, and calibrated IIP2 of the receiver are 4.5 dBm, −13.8 dBm, and 67.5 dBm, respectively. In the ADPLL, a calibration-free retiming fractional frequency dividing (FFD) scheme based on a parasitic insensitive digital phase interpolator is adopted, for releasing the narrow loop bandwidth limitation and achieving better phase noise without active noise cancellation techniques. In the DTX design, a piecewise bias voltage (PBV) technique is proposed for the AM-AM linearization. It achieves a peak output power of 22.5 dBm at 840 MHz with a drain efficiency of 60.2%. The DPA can work in a high-power mode without PBV and a middle-power mode with PBV for modulation with different complexity. Thanks to PBV, the DTX achieves 5.9%, 5.3% EVM for 2MS/s 16-QAM and 64-QAM without digital pre-distortion (DPD), respectively. The designed broadband reconfigurable transceiver can support most of the common IoT protocols in most key metrics.

A Gm-compensated 46-101 GHz broadband power amplifier (PA) for high-resolution FMCW radars is presented in this paper. For bandwidth (BW) expanding, a Gm compensator-based negative feedback chain is applied to the PA, compensating the large gain ripple caused by a high-k transformer (TF)-based ultra-wideband interstage matching network (IMN). Based on the proposed Gm-compensated technique, a flat and ultra-wideband power gain of the PA can be obtained with the high-k TF-based IMN. The proposed PA achieves a 55-GHz BW without additional area overhead and efficiency loss. 74.8% of the fractional BW is obtained with2.

A Quadrature/Polar hybrid digital transmitter architecture (HB-TX) is proposed in this paper, which consists of a main digital power amplifier (DPA), an auxiliary DPA, and a low-bit phase selector. In the proposed HB-TX, coarse polar modulation is realized by combining the main DPA and a low-bit selector, while a fine quadrature modulation is realized by the asymmetrical quadrature recombination of main and auxiliary DPAs in a small range. Through coarse and fine modulation, the HB-TX realizes fast signal modulation and does not require high-speed and high-resolution phase modulator. With the coarse polar modulation, the HB-TX achieves high efficiency which is close to that of polar transmitter and no longer suffers from 3 dB back-off. Since the asymmetry of two-path DPA arrays improves the isolation between two channels, local oscillators (LOs) with 50% duty cycle is employed to further improve the HB-TX's efficiency. Simulation results show that the HB-TX with a 4-bit selector achieves 23.7-dBm peak output power with 39.2% peak power added efficiency (PAE). When modulating a 64-QAM signal with 80-Msym/s symbol rate and 6.5-dB peak average power rate (PAPR), the HB-TX improves the average drain efficiency from 16.3% (achieved in quadrature transmitter) to 22.2% The average output power that is delivered by the HB-TX is 17.6-dBm with 17.4% average PAE, while the error vector magnitude (EVM) is -35.87 dB.

An 81-99 GHz tripler for wireless transceiver LO generation is presented in this paper. To suppress the fundamental signal and enhance the 3rd harmonic, the inversion signal is applied to the gate of the cascading transistor of the push-push differential pair. A capacitor is connected to the source and drain of the cascading transistor to further suppress the fundamental signal. Without additional filters, the tripler achieves more than 40 dBc of fundamental suppression with an even harmonic suppression of up to 60 dBc. The tripler reaches an output power of -2.6 dBm (4-dBm input) at 91.5 GHz with a 20% bandwidth of from 81 to 99 GHz. The core area of the chip occupies only 190 μm×530 μm in TSMC 40-nm CMOS process and consumes 28.2 mW.

This paper presents a fractional-N all digital phase locked loop (ADPLL) using a retiming high linear digital phase interpolator (DPI), which is free from pre- and background-calibration. The DPI utilizes a charge-sharing effect insensitive charge-based structure to improve the linearity. Designed in a 40-nm CMOS technology, the proposed DPI achieves 9-bit resolution, 0.3ps integral nonlinearity (INL) and 0.083ps differential nonlinearity (DNL). The proposed ADPLL achieves −118 dBc/Hz in-band phase noise at 1MHz and −93.9dBc fractional spur with the 0.3ps nonlinearity of DPI.

In wearable biomedical applications, a constant dc common-mode (CM) voltage of low-pass filters (LPFs) is needed to boost the dynamic range when low supply voltage is used for high power efficiency. Traditional source-follower based LPFs consume very low power but introduce a CM voltage difference between input and output. This paper presents an ultra-low-power LPF, which features a source-follower based topology with a bulk-feedback technique. The bulk-feedback technique is proposed to keep a constant dc CM voltage, which is robust to process and temperature variations. In order to validate the proposed concept, a fourth-order LPF has been designed as a prototype. Implemented in a TSMC 180 nm CMOS process, the filter occupies an active area of only 0.048 mm2. Simulation results show that the filter consumes 9.0-nW static power from a 0.5-V voltage supply when the cutoff frequency is set to about 200 Hz. The filter achieves an input-referred noise in -3 dB bandwidth of 41.21 μVrms and an in-band IIP3 of 4.0 dBV, which corresponds to a spurious free dynamic range (SFDR) of 61.1 dB. The proposed LPF achieves a competitive FOM among the reported works.

This paper presents an 8-bit calibration-free LO-path phase shifter (PS) for large scale 28 GHz phased-array transceiver. To overcome the nonlinearity of a vector-summing PS, two 8-bit digitally-controlled variable gain amplifier are utilized to generate high linearity amplitude modulation. Three transformers cooperating with a parallel resonator are developed to sum the I/Q signal as well as provide a fine isolation between I/Q path, thus provide a high linearity vector summation. Simulation results show that the PS achieves 360° phase shift with 8-bit resolution and a RMS phase error of 0.51°. The INL and DNL of phase-shifting is +0.66°/-0.83° and +0.22°/-0.19° respectively. Implemented in TSMC 40 nm LP process, the chip occupies an active area of 0.18 mm2and consumes 28.6 mW from 1.1 V supply voltage.

This paper proposes a 2.4 GHz ultra-low power pseudo-backscatter modulator with an integrated directional coupler for wireless sensor network applications. In order to improve the performance of backscatter modulator for multilevel modulation, an integrated directional coupler is employed to isolate the radio frequency carrier wave from the modulated signal. As a result, the carrier wave can be modulated in radio frequency domain independently without being affected by reflection coefficient of a conventional backscatter modulator. For further reducing power dissipation, the modulator only employs buffers for output and implements modulation by passive circuits. The proposed modulator is demonstrated in a standard 40 nm CMOS 1P10M process and it achieves 64-QAM modulation at 3 Mb/s data rate by consuming only 43.2 μW with a supply voltage of 0.8 V.

A 12-bit 2.5GHz digital-to-time converter (DTC) for high resolution and high linearity applications is presented in this paper. The DTC is segmented into a 4-bit coarse stage and an 8-bit fine stage. The proposed fine stage utilizes parasitic-insensitive charge-based (PICB) phase interpolator (PI) with significant improvement in linearity. The PICB PI outputs 50% duty cycle differential clock and its performance is insensitive to parasitic effect. The DTC is designed in 40nm CMOS technology and consumes 7.1mW with a 1.1-V supply voltage. Simulation results show that the peak integral nonlinearity and differential nonlinearity are 0.37ps and 0.085ps, respectively.

This paper presents a low power SAW-less 2.4-GHz receiver for short-range communications. To ensure sufficient out-of-band (OOB) linearity for SoC existence, a LC matched series N-path filter based receiver topology is proposed. The radio frequency input is followed by the LC matched series N-path filter, which provides sufficient ultimate rejection when consuming less power than conventional N-path filters. An on-chip inductor and a capacitor are utilized to achieve input matching and improve the NF. Implemented in TSMC 40nm LP process, the chip occupies an active area of 0.312 mm2. Simulation results show that the receiver consumes 2.2 mW from 1.1V supply voltage with a NF of 6.3 dB (with the on-chip inductor) and a voltage gain of 38.4 dB. The baseband achieves a third order filtering response with 1.5 MHz bandwidth. The OOB 1-dB compression point is +7 dBm and the OOB IIP3 is +22 dBm.

In this paper, a novel combinational access topology of Tunnel FET (TFET) SRAM is proposed for ultra-Low Power applications. Since forward p-i-n current of TFET could cause serious damage to SRAM circuit performance, the proposed topology can avoid the forward bias applied to the p-i-n junction, thus increasing SRAM cell read and hold static noise margin (SNM) and decreasing its static power consumption dramatically. At 0.6 V supply voltage, the combinational access TFET SRAM topology presents 26% hold SNM larger than traditional TFET SRAM topologies, 8 orders of magnitude lower static power consumption, and 2 order of magnitude lower power delay product, demonstrating its great potential for ultra-low power applications.

This paper presents a MICS/ISM band receiver for ultra-low-power applications with a passive RF front-end. A shunt passive mixer along with low input capacitance amplifiers is introduced to decrease the large load capacitor and minimize power consumption of the Local Oscillator (LO) buffers without significant noise figure (NF) degradation. Measurement results show that the receiver consumes 89 μW from 1 V supply voltage with a NF of 7.5 dB and a voltage gain of 47.6 dB. S112.