We present an LC-based hybrid sub-sampling phase-locked loop (PLL). A novel tri-state integral path is applied to reduce the loop filter (LF) area and eliminate ripples on the control signals. The effectiveness of the proposed technique is compared with type-II hybrid PLL and PLL using delta-sigma modulator. The 24.6-29.6GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of 44fs and -254.8dB FOM and consumes power of 17mW from a 0.9/0.95V supply.

This article investigates the multirobot efficient search (MuRES) for a nonadversarial moving target problem from the multiagent reinforcement learning (MARL) perspective. MARL is deemed as a promising research field for cooperative multiagent applications. However, one of the main bottlenecks of applying MARL to the MuRES problem is the nonstationarity introduced by multiple learning agents. With learning agents simultaneously updating their policies, the environment cannot be modeled as astationaryMarkov decision process, which results in the inapplicability of fundamental reinforcement learning techniques such as deep$Q$-network and policy gradient (PG). In view of that, we adopt the centralized training and decentralized execution scheme and thereby propose a cross-entropy regularized policy gradient (CE-PG) method to train the learning agents/robots. We let the robotscommitto a predetermined policy during execution, collect the trajectories, and then perform centralized training for the corresponding policy improvement. In this way, the nonstationarity problem is overcome, in that the robots do not update their policies during execution. During the centralized training stage, we improve the canonical PG method to consider the interactions among robots by adding a cross-entropy regularization term, which essentially functions to “disperse” the robots in the environment. Extensive simulation results and comparisons with state of the art show CE-PG's superior performance, and we also validate the algorithm with a real multirobot system in an indoor moving target search scenario.

We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The 10-GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of}299.5 fs and power of 9.9 mW from a 1-V supply.

Analog and mixed-signal (AMS) blocks are often a crucial and time-consuming part of System-on-Chip (SoC) design, primarily due to a manual circuit and layout iterations. Existing automated solutions for selecting circuit parameters for a given target specification are often not efficient, accurate, or reliable. In order for an automated sizing tool to be practical, we posit that it must: 1) return valid results for a large range of target specifications; 2) understand where and why it is unable to meet certain specifications; 3) consider true layout parasitic simulations for complete end-to-end design; and 4) be automated, allowing most of the design effort to fall on the tool. In this article, we address these critical points by establishing an automated reinforcement learning framework, AutoCkt, by 1) successfully deploying it on a complex two-stage transimpedance amplifier and two-stage folded cascode with biasing in the 16-nm FinFet technology; 2) implementing a new combined distribution deployment algorithm to improve efficiency; 3) analyzing in-depth the efficacy of the trained agent; and 4) demonstrating the functionality of this tool when considering a topology that is highly sensitive to layout parasitics. Our algorithm not only successfully reaches unique, valid, and practical performances, but also does so in state-of-the-art run time, up to 38X more efficient than prior work. In addition, our tool averages just four parasitic simulations obtained by using the Berkeley Analog Generator, to achieve a target specification post-layout for the folded cascode. AutoCkt successfully generates LVS-passed designs with validation in process corner variation results.

We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.

This paper presents a high-precision, low temperature coefficient (TC) CMOS bandgap reference for high-performance multi-channel ADC working under wide temperature range. A piecewise curvature compensation technique is proposed to extend its operating temperature range and keep its low temperature coefficient. A ß-compensation technique is used to cancel the PTAT and non-PTAT spread of the output due to variation of β in the BJTs. Moreover, the trimming resistors are implemented to calibrate the 1st-order temperature coefficient and absolute value of the output voltage. The bandgap reference designed in 0.18μm CMOS process has a super low temperature coefficient of 2.1ppm/°C over a wide temperature of −55 ° C to 140 ° C, making it appropriate to provide reference voltage for a high-precision ADC.