This work presents the design and validation of a Voltage Controlled Current Source (VCCS) aiming the Electrical Bio-Impedance Spectroscopy (EBS) application for Cervical Cancer Detection (CCD). Its topology relies on a modified variety of the classical Howland Current Source, whose schematic and layout were performed in the TSMC 65 nm CMOS process at a standard 1.2 V power supply. In this application, a stable sinusoidal load current must be provided with an amplitude of 10 μA to comply with international electromedical apparatus’ norms (IEC-60601-1) over a wide range of tissue impedance. Therefore, an advanced four-stage Operational Amplifier was customized to fulfill the VCCS’ requirements. The most noteworthy design outcomes were: a robust linearity, compatible with a subsequent 10-bit ADC sampling; a high output impedance, ranging from 1.59 GΩ at 100 Hz up to 159 kΩ at 1 MHz; an AC current amplitude consistently approaching 10 μA with a low DC offset of about ±1 μA for both 10 Ω and 5 kΩ loads at 1 MHz in Monte Carlo simulations; a compact area of 286x82 μm2(without pads); a power dissipation close to 3.7 mW. Consequently, the obtained specifications position the proposed VCCS as an extremely prominent block suitable to be utilized for EBS/CCD.

This paper presents an improved baseline correction filter to be used in the readout front-end ASICs of gaseous detector systems in high energy physics experiments. The digital filter is based on an FIR section and used in the data pipeline running in real-time thought the input signals, allowing adequate data compression by the subsequent blocks in the processing chain. The proposed design was optimized to cope with the power and area trade-offs while hardening the block using redundancy and a novel automated design system based on artificial intelligence. This optimizer is also discussed including its logic and improvements using genetic algorithms with dynamic mutation and cross-over probabilities connected to run-time EDA tools. The designed filter was fabricated in 130 nm process, packaged and tested in the Peletron particle accelerator at the University of Sao Paulo. The device was irradiated and received a total dose of 70 krad during about one week of exposition to alpha particles without any measured failure, validating the design and solving the vulnerability with a small increase in the channel area of just 0.07%.

This work presents the design and experimental results of a current mode Scalable Low-Voltage Signaling (SLVS) transceiver in 130 nm CMOS technology. The proposed transmitter includes a feedback control which reduces the common-mode voltage variations in terms of the Vds voltage of the bias transistor, and an enable/disable operation mode, which minimizes the power consumption when data transmission is not requested. A rail-to-rail comparator topology was used to design the receiver circuit being robust to transient common-mode variations with low power consumption and high speed. The experimental DC power consumption of the transceiver is 4.6 mW at 1.25V power supply, where 1.1 mW is consumed by the receiver and 3.5 mW by the transmitter. The eye diagram proves the proper dynamic operation of the circuit until a data rate of 1.2Gbps.