The growing number of security threats and vulnerabilities in automotive and industrial control systems motivates the design of Controller Area Network (CAN) bus components with enhanced security measures while maintaining compatibility with existing standards and allowing for interoperability with non-enhanced systems. We present such an enhancement that is implemented by replacing standard CAN bus transceivers with a new transceiver that permits automatic authentication of CAN frames. The theoretical basis of our approach is based on incorporating a secondary communications channel in a virtual manner that simultaneously transmits an authentication signature with each CAN frame. To implement the authentication mechanism, a new backward-compatible transceiver is described, designed and validated that implements the virtual channel through selectively delaying the rising edges in a Non-Return-to-Zero (NRZ) waveform that encodes a CAN frame at the physical layer. Novel aspects of the CAN transceiver include the use of use of authentication signature generators and comparators, rising edge time-based modulator/demodulator circuitry, and phase-preserving rail converters. The mixed-signal transceiver circuit was fabricated using a$0.18\mu $m CMOS process and operation was validated over PVT corner cases and with non-secure transceivers to demonstrate backward compatibility.

A new CAN bus transceiver integrated circuit is described that incorporates an inherent auxiliary data channel. The auxiliary data channel enables CAN packet authentication signatures to accompany primary data payloads. The transceiver is backward compatible with the CAN protocol and thus may be used within existing networks with no modifications required. The clock edge at the transmitter is phase modulated with signature data in a manner that does not exceed clock jitter tolerances in the CAN specifications. The receiver is designed to recover the primary data and the packet signature. By comparing the received signature with the authorized packet signature, a “Go/No Go” output indicates if the received packet is properly authenticated.

We present an RF sampling 1 GS/s 12-bit single-channel successive approximation register (SAR) assisted pipeline analog to digital converter (ADC). A novel Harmonic-injecting Cross-Coupled Pair (HXCP) is proposed in a$\text{G}_{\text {m}}$-R based residue amplifier design as a critical part of the presented ADC. This technique overcomes the challenges in designing analog amplifiers using advanced nanometer CMOS processes and achieves the gain and linearity required for the ADC. By implementing the HXCP in a residue amplifier (RA), the proposed technique successfully improves the RA linearity by at least 10 dB and meanwhile boosts the gain of the RA to be about 8. The entire ADC consists of three stages each with 4-bit, 4-bit, and 6-bit, respectively. Two one-bit interstage redundancies are implemented between the three stages. Various techniques are also implemented to help the ADC achieve the targeted speed and resolution. The presented ADC was implemented in a 28nm CMOS process and achieves an ERBW of 1 GHz, an SNDR of 60.7 dB, an SFDR of 73 dB at Nyquist input (495 MHz) and an SFDR of 82 dB at 1 GHz input. A 7.5 fj/conv-step FoMwand a 169.4 dB FoMs are achieved, which demonstrate one of the best Figure of Merits (FoMs) among ADCs of similar speed and resolution.

This article presents a 2.56-GS/s 12-bit eight-channel interleaved analog-to-digital converter (ADC) that achieves an FOM$_{S}$of 156.6 dB at near the Nyquist input frequency of 1.2 GHz in 65-nm CMOS technology. A new technique is employed to mitigate the effect of comparator metastability. In addition, a noise averaging calibration method is implemented to calibrate the comparator offset in each subchannel in the foreground. Moreover, a digital-to-time delay tuner is employed to minimize the time skew among the eight channels. Several other calibration techniques are also employed to reduce the interchannel and intrachannel nonidealities. The single subchannel ADC achieves an SNDR of 59.6 dB and an FOM$_{S}$of 167.3 dB at the Nyquist input frequency with a sampling rate of 350 MS/s. With eight subchannels interleaved, the 2.56-GS/s ADC achieves an SNDR of 55.7 dB and an SFDR of 64 dB at the Nyquist input with calibration. In addition, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the interleaved ADC are 0.51/−0.4 LSB and +1.38/−0.89 LSB, respectively.

FPGAs are becoming an attractive choice as a heterogeneous computing unit for scientific computing because FPGA vendors are adding floating-point-optimized architectures to their product lines. Additionally, high-level synthesis (HLS) tools such as Altera OpenCL SDK are emerging, which could potentially break the FPGA programming wall and provide a streamlined flow for domain experts in scientific computing. On the other hand, providing high performance in the presence of irregular memory access patterns to off-chip memory remains a challenge for the automated synthesis flows. In this paper, we study the performance/energy characteristics of OpenCL-generated FPGA designs on irregular memory access patterns, targeting XSBench, a memory-intensive Monte Carlo simulation code, as a case study. To complete our study, we implement XSBench in OpenCL and study optimization strategies for FPGAs. We observe that our OpenCL implantation of XSBench achieves 50 % higher energy efficiency on an Intel Arria10-based FPGA platform than that on an Intel Xeon 8-core CPU while trading off 35 % of performance.