This paper presents a fully integrated NMOS stimulator using a hybrid dynamic bulk biasing technique (HDBT) and a charge-pump-like control technique (CCT) in a 180-nm bulk CMOS technology. HDBT integrates terminal-voltage-dependent and logic dynamic bulk biasing to set the bulk bias voltage according to the electrode voltage. CCT adds a DC voltage to the gate terminal through a diode and capacitor to help turn on the NMOS transistor. It helps turn off the transistor by shorting the source and gate terminals together and applying two diodes across the drain and source terminals. To achieve an electrode voltage higher than the breakdown voltage of substrate diode ($V_{\mathrm {BD}}$) with an independent power supply, a high voltage tolerant switch is proposed with HDBT and CCT. A high voltage interface is also proposed, utilizing the capacitor adaptive biasing, to overcome the limitation of$V_{\mathrm {BD}}$between the high and low voltage domains and to accommodate the variation of electrode voltage. Fabricated in a 180-nm standard CMOS technology, the stimulator achieves a maximum electrode voltage ($V_{\mathrm {E,MAX}}$) of 18.74V under a 3.3-V supply, with a highest$V_{\mathrm {E,MAX}}$/$V_{\mathrm {BD}}$ratio of 1.27 than state-of-the-art stimulators, including non-standard technology designs. In a continuous output test mode over 10million cycles, the variation of$V_{\mathrm {E,MAX}}$is less than 150mV. The measured maximum residual voltage on the capacitor is 13.55mV.

This paper presents a hybrid all-NMOS rectifier with two gate-biasing techniques to extend the power dynamic range (PDR) for wireless power transfer. The proposed hybrid rectifier combines the strengths of the cross-connected (CC) and diode-based (DB) configurations, achieving both a high forward current and a small reverse current along the PDR. Additionally, two separate gate-biasing techniques are employed to optimize the gate bias voltage for the gate-biased-CC and gate-biased-DB parts, respectively. All transistors in the rectifier are NMOS transistors, which can minimize the total area when extended to multi-stage configurations. The circuit is implemented in a 180-nm CMOS process, occupying an area of 0.195 mm2. Experimental results show a sensitivity of -10.3 dBm with a 1 MΩ load and a peak power conversion efficiency of 78.6% at -7.4 dBm with a 3 kΩ load. In addition, the proposed rectifier achieves a PDR greater than 22.3 dB with loads below 5 kΩ.

This paper presents a monopolar neural stimulator using dynamic current replication technique based on switched-capacitor sampling. It employs dynamic current mirror circuits as the current source and the current sink to overcome the impact of process variation on current matching, achieve good charge balance and ensure the security of the monopolar neural stimulator. The proposed monopolar stimulator is implemented with a 0.18-μm 1.8 V/3.3 V standard CMOS process. The simulated results indicate that the current mismatch between the cathodic and anodic current is less than 0.21%, and the charge mismatch is below 0.33% within the entire stimulus current range (0.3 mA ~ 3 mA). The corresponding maximum residual average DC current error with shorting electrode discharge is less than 1 nA.

In this paper, a switched Z-source dc-dc converter (SZSC) is proposed for the conversion from a low voltage to a higher one in renewable energy systems. The voltage gain is increased by adding another one switch and diode to the output terminal of the traditional Z-source dc-dc converter. Not only does the output capacitor function as the filter capacitor; it is also connected in series into the inductors' charging loops when both switches are turned on. Compared with existing Z-source based structures, higher voltage gain is realized with a small duty ratio (smaller than 25%), which can avoid the instability caused by saturation of inductors. Fewer passive components are employed when compared with the recently proposed hybrid Z-source topologies that have the same boost factor, increasing the efficiency and decreasing the cost. Another two switched quasi-Z-source dc-dc converters (SQZSCs) with the same transfer ratio are proposed in analog to the two traditional quasi-Z-source topologies. The performances of the proposed SZSC are analyzed, and then validated by simulation and experimental results.

In this paper, a quasi-resonant switched-capacitor (QRSC) multilevel inverter (MLI) is proposed with self-voltage balancing for single-phase high-frequency ac (HFAC) microgrids. It is composed of a QRSC circuit (QRSCC) in the frontend and an H-bridge circuit in the backend. The input voltage is divided averagely by the series-connected capacitors in QRSCC, and any voltage level can be obtained by increasing the capacitor number. The different operational mechanism and the resulting different application make up for the deficiency of the existing switched-capacitor topologies. The capacitors are connected in parallel partially or wholly when discharging to the load, thus the self-voltage balancing is realized without any high-frequency balancing algorithm. In other words, the proposed QRSC MLI is especially adapted for HFAC fields, where fundamental frequency modulation is preferred when considering the switching frequency and the resulting loss. The quasi-resonance technique is utilized to suppress the current spikes that emerge from the instantaneous parallel connection of the series-connected capacitors and the input source, decreasing the capacitance, increasing their lifetimes, and reducing the electromagnetic interference, simultaneously. The circuit analysis, power loss analysis, and comparisons with typical switched-capacitor topologies are presented. To evaluate the superior performances, a nine-level prototype is designed and implemented in both simulation and experiment, whose results confirm the feasibility of the proposed QRSC MLI.