Phase transition materials (PTMs) have drawn significant attention in recent years due to their abrupt threshold switching characteristics and hysteretic behavior. Augmentation of the PTM with a transistor has been shown to provide enhanced selectivity (as high as ~107 for Ag/HfO2/Pt) leading to unique circuit-level advantages. Previously, a unipolar PTM, Ag-HfO2-Pt, was reported as a replacement for diodes due to its polarity-dependent high selectivity and hysteretic properties. It was shown to achieve ~50% higher-DC output compared to a diode-based design in a Cockcroft-Walton multiplier circuit. In this article, we take a deeper dive into this design. We augment two different PTMs (unipolar Ag-HfO2-Pt and bipolar VO2) with diode-connected MOSFETs to retain the benefits of hysteretic rectification. Our proposed hysteretic diodes (Hyperdiodes) exhibit a low-forward voltage drop owing to their volatile hysteretic characteristics. However, augmenting a hysteretic PTM with a transistor brings an additional stability concern due to their complex interplay. Hence, we perform a comprehensive stability analysis for a range of threshold voltages (−0.2 V$V_{\mathrm { th}}$$3 {\sigma }$Monte-Carlo variation analysis for a Cockcroft-Walton multiplier considering the nonidealities in the host transistor and the PTM. We observe that, hyperdiode-based design achieves ~20% higher-output voltage compared with the conventional designs within a fixed timeframe ($200~\boldsymbol {\mu }$s).

This report presents a design space analysis for the phase transition material (PTM)-augmented magnetic random-access memories (MRAMs) with separate read–write paths. PTM is augmented in parallel with the magnetic tunnel junction (MTJ), improving the read performance along with providing separate read–write paths. Compared to the standard MRAM, PTM-augmented design achieves up to$1.7 \times $boost in cell tunnel magnetoresistance (CTMR),$1.2 \times $increase in read disturb margin (RDM), and${\sim }3.75 \times $increase in sense margin (SM) at the cost of${\sim }4.75 \times $more power consumption. Here, we first discuss the operating region and biasing requirements to achieve performance improvement. Then, we thoroughly explore the design space to put more options on the table for choosing the material and device structure. Finally, we perform the variation analysis where we address the performance and variation immunity tradeoffs. We demonstrate a 1000-point Monte-Carlo analysis to illustrate the effects of process variations on the performance. With lower distinguishability and read stability, the variation tolerance of the design can be improved manifold employing device-circuit co-design methodology and vice versa.

Spiking neural network (SNN) has emerged as the most biologically accurate approach for information encoding in neuromorphic computing. Cryogenic neuromorphic hardware, which offers exceptional energy efficiency and speed, has recently gained enormous attention among the neuromorphic community. An approach to build such neuromorphic hardware is to use a conductance asymmetric superconducting quantum interference device (CA-SQUID) that has non-volatile and variation- robust dual-resistive behavior and thereby, is referred to as a superconducting memristor (SM). Here, we utilize this unique device to design an SM-based artificial synapse topology for neuromorphic applications. The proposed synapse structure, combined with an SM-based neuron, demonstrates neurosynaptic behavior with enhanced reconfigurability. Our design features eight different non-volatile levels of synaptic strength, utilizing combinations of distinct resistance levels of three SMs, exhibiting an estimated programming power of 8.5 pW. This weight storage feature enables better reconfigurability compared to the existing superconducting synapse structures that utilized fixed resistors and inductors. Additionally, this synapse can be further fine-tuned to dynamically access a wide range of synaptic strengths by using an external bias current. Our study provides valuable insights into the system-level integration of the neuron-synaptic architecture.

By taking inspiration from the operation of biological brains, emerging brain-inspired hardware has the potential to revolutionize the way computations are performed. Brain-inspired computing can be realized using both classical CMOS and emerging beyond-CMOS technologies, whereas the latter holds the promise to provide substantial energy savings akin to the employment of non-volatile memories. One way to implement highly efficient brain-inspired AI applications is through analog computing schemes, such as Integrate-and-Fire (IF) Spiking Neural Networks (SNNs), which can be implemented using both CMOS and beyond-CMOS technologies as synaptic storage. However, managing the inherent degradation of computing accuracy in analog circuits and mitigating their effects on the predictive accuracy of AI systems remains a key challenge due to the inherent nature of analog computing.In this paper, we discuss how the aforementioned challenges can be addressed. In the first part, we present our SPICE-Torch, a framework that connects low-level SPICE simulations of circuits and memories performing analog computations with high-level accuracy evaluations of NN models based on PyTorch. Furthermore, we present an example of neuromorphic optimization using classical CMOS technology. In the second part, we introduce memristors as an emerging beyond-CMOS technology that can retain their state without any outside influence and are well-suited for brain-inspired neuromorphic hardware. We demonstrate that brain-inspired hardware, realized using classical CMOS or beyond-CMOS technologies, has the potential to revolutionize the way we process information and solve complex computation problems. Nevertheless, to harness its full potential, reliability issues have to be managed carefully and HW/SW codesign is key. Our presented framework SPICE-Torch, which connects low-level SPICE simulations of circuits performing analog computations with high-level accuracy evaluations of NN models based on PyTorch is available as open-source in https://github.com/myay/SPICE-Torch.