This paper addresses the challenges in accurate and real-time traffic congestion prediction under uncertainty by proposing Ising-Traffic, a dual-model Ising-based traffic prediction framework that delivers higher accuracy and lower latency than SOTA solutions. While traditional solutions face the dilemma from the trade-off between algorithm complexity and computational efficiency, our Ising-based method breaks away from the trade-off leveraging the Ising model's strong expressivity and the Ising machine's strong computation power. In particular, Ising-Traffic formulates traffic prediction under uncertainty into two Ising models: Reconstruct-Ising and Predict-Ising. Reconstruct-Ising is mapped onto modern Ising machines and handles uncertainty in traffic accurately with negligible latency and energy consumption, while Predict-Ising is mapped onto traditional processors and predicts future congestion precisely with only at most 1.8% computational demands of existing solutions. Our evaluation shows Ising-Traffic delivers on average 98X speedups and 5% accuracy improvement over SOTA.

Due to the Ising model’s strong expressivity and Ising machines’ unique computational power, it is highly desired if Ising-based learning can be used in real-world applications. Unfortunately, the challenges in learning the Ising model and gaps between the practical accuracy of Ising machines and the theoretical accuracy of the Ising model impede the realization of Ising machines’ potential. Hence, we propose an Ising Machine Learning framework, Ising-CF, for collaborative filtering, a widely-used recommendation method. Specifically, Ising-CF uses Linear Neural Networks with Besag’s pseudo-likelihood and voltage polarization for fast, accurate Ising model learning and an Ising-specific logarithmic quantization for ns-level Ising machine inference with near-theoretical accuracy, 7.3% over SOTA.

A prominent approach to solving combinatorial optimization problems on parallel hardware is Ising machines, i.e., hardware implementations of networks of interacting binary spin variables. Most Ising machines leverage second-order interactions although important classes of optimization problems, such as satisfiability problems, map more seamlessly to Ising networks with higher-order interactions. Here, we demonstrate that higher-order Ising machines can solve satisfiability problems more resource-efficiently in terms of the number of spin variables and their connections when compared to traditional second-order Ising machines. Further, our results show on a benchmark dataset of Boolean \textit{k}-satisfiability problems that higher-order Ising machines implemented with coupled oscillators rapidly find solutions that are better than second-order Ising machines, thus, improving the current state-of-the-art for Ising machines.

Physical Ising machines have been shown to solve combinatoric optimization problems with orders-of-magnitude improvements in speed and energy efficiency o ver v on N eumann systems. However, building such a system is still in its infancy and a scalable, robust implementation remains challenging. CMOS-compatible electronic Ising machines (e.g., [1]) are promising as the mature technology helps bring scale, speed, and energy efficiency to the dynamical system. However, subtle issues can arise when using voltage-controlled transistors to act as programmable resistive coupling. In this paper, we propose a version of resistively-coupled Ising machine using quantized nodal interactions (QuBRIM), which significantly i mproved the predictability of the coupling resistor. The functionality of QuBRIM is demonstrated by solving the well-known Max-Cut problem using both behavioral and circuit level simulations in 45 nm CMOS technology node. We show that the dynamical system naturally seeks local minima in the objective function's energy landscape and that by applying spin-fix a nnealing, t he system reaches a global minimum with a high probability.

Nature has inspired a lot of problem solving techniques over the decades. More recently, researchers have increasingly turned to harnessing nature to solve problems directly. Ising machines are a good example and there are numerous research prototypes as well as many design concepts. They can map a family of NP-complete problems and derive competitive solutions at speeds much greater than conventional algorithms and in some cases, at a fraction of the energy cost of a von Neumann computer.

Understanding program behavior is at the heart of general-purpose architecture design. Whether we are testing a new design offline or making a design adapt to changing behavior online, a central assumption is that the test cases represent real workload in steady state. Typical computer programs have been known to exhibit patterns of runtime behavior that repeat during the course of their execution. Simulation and adaptation strategies all exploit this repetition to some extent. In this paper, we introduce a simple mechanism that is more explicit in identifying and exploiting behavior repetition at the granularity of (broadly defined) loops. The result is that a typical benchmark will be categorized into tens of loops. In terms of architectural simulations, this strategy will create a moderate number (on the orders of 100) of relatively short (tens of thousands of instructions) segments. There are two major benefits in our view. The first and more quantifiable benefit is that, the strategy requires less simulation and obtains increased accuracy compared to the commonly used SimPoint approach. Second, instead of depicting average statistics of an entire program, we can accurately describe intra-program behavior variation, which simple sampling strategies cannot. LoopIn produces many small simulation segments. In certain usage scenarios, microarchitectural state warm-up may be costly. In these cases, an existing tool BLRL can help create efficient warm-up arrangements.

Chip manufacturers are constantly trying to increase the on-chip compute power to meet the ever increasing compute demands of modern computer applications. Such high compute power processor architectures often require a steady supply of large amounts of data to be able to make full use of their raw compute power. Historically, memory technologies have lagged behind the processors in terms of speed. So, memory bandwidth often becomes a performance limiter. Higher memory bandwidth also leads to an increase in the overall energy and power consumption of the system. As a result, reducing off-chip data traffic continues to be an important design problem for future processor architectures. In this paper, we identify a portion of off-chip traffic produced by modern graphics applications that can be avoided while maintaining functional correctness. We note that modern graphics applications produce a lot of intermediate data and that this intermediate data serves no purpose or becomes irrelevant after the application has consumed it. We show that a significant portion of the off-chip traffic is produced by this irrelevant intermediate data. We also propose a mechanism with which this off-chip traffic could be significantly reduced.