Analog compute-in-memory (ACIM) architectures emerged as energy efficient matrix–vector multiplication accelerators utilized for neural network inference in power-constrained environments. However, the security implications of ACIM hard-ware remain almost entirely unexplored. In particular, no previous work has evaluated information leakage of fabricated ACIM hardware through power side-channels. This work presents the first measured power side-channel analysis of a fabricated 28 nm ACIM macro. Using a convolutional neural network (CNN) work-load, we show that power traces exhibit strong data-dependent information leakage that allows accurate reconstruction of private input images, with a mean structural similarity index measure (MSSIM) of up to 0.71.

Side-channel attacks represent a significant and persistent threat to hardware security. One effective strategy for safeguarding hardware components against these attacks involves the implementation of masking schemes. Among these schemes, Inner Product Masking (IPM) has received considerable attention and analysis in prior research. Inner Product Masking with Error Detection aims to extend the security provided by IPM to Fault-Injection attacks. This can be achieved by incorporating (linear) repetition code for fault detection (IPM-FD) or by integrating a non-linear robust error detection into the scheme (IPM-RED). IPM-RED can detect (with non-zero probability) every fault regardless the number of bits it flips. However, this robustness comes with a cost, a non-linear function may leak via the physical channels more information than a linear one. This paper shows that information leakage from IPM-RED is marginal. An improved IPM-RED masking scheme is also presented, and an empirical side-channel leakage analysis of the protected Advanced Encryption Standard (AES) design utilizing the Test Vector Leakage Assessment (TVLA).

The security of computer systems can be increased effectively by using cryptographic co-processors to encapsulate secrets and speed-up the computationally intensive cryptographic functions. This can be especially advantageous for Internet of Things devices, as they usually have to be very efficient in cost, space and timing. However, these devices are also at greater risk of becoming targets of hardware attacks, as they handle sensitive data and are physically exposed to a nearly unrestricted population of users. This paper describes a modular cryptographic co-processor, allowing it to be applied in different scenarios and easily adjusted to concrete system specifications. The co-processor design is also open-source and freely available for anyone to further applications and modifications. It implements the basic cryptographic functions of symmetric encryption, hashing and a pseudo random number generation, with an interface to a true random number generator. In addition, the co-processor offers additional interfaces for key generation. A specific realization is presented in detail, compared to existing solutions, and its resilience against various attacks is discussed.

The evaluation of fault attacks on security-critical hardware implementations of cryptographic primitives is an important concern. In such regards, we have created a framework for automated construction of fault attacks on hardware realization of ciphers. The framework can be used to quickly evaluate any cipher implementations, including any optimisations. It takes the circuit description of the cipher and the fault model as input. The output of the framework is a set of algebraic equations, such as conjunctive normal form (CNF) clauses, which is then fed to a SAT solver. We consider both attacking an actual implementation of a cipher on an field-programmable gate array (FPGA) platform using a fault injector and the evaluation of an early design of the cipher using idealized fault models. We report the successful application of our hardware-oriented framework to a collection of ciphers, including the advanced encryption standard (AES), and the lightweight block ciphers LED and PRESENT. The corresponding results and a discussion of the impact to different fault models on our framework are shown. Moreover, we report significant improvements compared to similar frameworks, such as speedups or more advanced features. Our framework is the first algebraic fault attack (AFA) tool to evaluate the state-of-the art cipher LED-64, PRESENT and full-scale AES using only hardware-oriented structural cipher descriptions.

A prototype of the framework AutoFault, which automatically constructs fault-injection attacks for hardware realizations of ciphers, is presented. AutoFault can be used to quickly evaluate the resistance of security-critical hardware blocks to fault attacks and the adequacy of implemented countermeasures. The framework takes as inputs solely the circuit description of the cipher and the fault(s) and produces an algebraic formula that can be handed over to an external solver. In contrast to previous work, attacks constructed by AutoFault do not incorporate any cipher-specific cryptoanalytic derivations, making the framework accessible to users without cryptographic background. We report successful application of AutoFault in combination with a state-of-the-art SAT solver to LED-64 and to small-scale AES. To the best of our knowledge, this is the first time that a state-of-the-art cipher (LED-64) was broken by a fault attack with no prior manual cryptanalysis whatsoever.