Lithography compliance is required to guarantee manufacturability of advanced integrated circuits. Conventional flow to enhance lithography printability relies on techniques like OPC and SRAF which happen at mask design. The optimization space at such a late design stage can be extremely limited due to fixed placement and routing solutions after layout design. In this work, we aim at optimizing lithography printability at early design stages and propose a post-routing layout optimization framework to enlarge lithography process window. The framework leverages a transformer-based deep learning model for fast process window evaluation and simultaneously modifies the layout patterns for lithography compliance, while subjecting to design rules and connectivity constraints. The experimental results exemplify the capability of exploiting our framework to improve the lithography window by an average of 4.31%. Furthermore, the framework greatly improves optimization for layouts with hotspots.

Lithography compliance is critical to the manufacturability of modern integrated circuits. Applying resolution enhancement techniques like OPC and ILT at sign-off stages is too late and can only make minor layout adjustment, which has limited optimization space to improve printability in advanced technology nodes.

With the continuous shrinking of feature size, directed self-assembly (DSA) has gradually become one of the leading candidates for extending the resolution of optical lithography to sub-7 nm and beyond, a DSA-based extra via (EV) insertion scheme is the key to guarantee the reliability of integrated circuit when applying DSA during manufacturing. In this paper, we proposed an automatic insertion algorithm of extra via taking the manufacturing cost of the guiding template in DSA into consideration in the EV insertion process, which makes the total cost of subsequent DSA-MP hybrid lithography controllable, while maintaining a high insertion rate of EV. The simulation results show that, with the same experimental patterns, the insertion rate of EVs is increased by about 10% compared with the previous integer linear programming method.

Layout hotspot detection is one of the most important issues for the reliability enhancement of integrated circuits. Machine learning-based hotspot detectors have shown their advantages of efficiency and generalization compared with computationally intensive lithography process simulation. However, most machine learning-based hotspot detectors only accept layout clips of fixed size as input with the potential defect whose location is restricted at the center of each clip. Therefore, they cannot be used directly for multiple hotspots detection in a large area, which occurs frequently in real design cases. In this article, we build a new end-to-end hotspot detector based on a fully convolutional network, which has the flexibility of detecting a various number of hotspots in a layout of any size at one time. Moreover, we also develop a transfer learning scheme matching our proposed detector network, which can reduce the requirement of sample number when setting up a new model for a more advanced technology node. The experimental results demonstrate our proposed hotspot detector outstanding among state-of-the-art works and the transfer learning scheme is effective.