A CMOS wideband voltage-mode fully differential all-pass filter (APF) is discussed. The APF circuit consists of three transistors, two inductors, two capacitors, and four resistors. The proposed APF employs the generic two-transistor common-source amplifier structure. Design procedures along with parasitic analysis are presented for wideband applications. The proposed APF is designed and fabricated in a 65-nm CMOS process. The operation of the proposed APF is validated by experimental and post-layout simulation results. The filter experimentally demonstrates a group delay (GD) of 59 ps at 26 GHz and it has less than 10% delay variation across a wide bandwidth of 24-29 GHz. The implemented design occupies an area of 0.09 mm2and consumes 5.1 mA from 1 V supply voltage. The noise and linearity performances of the proposed APF are validated by post-layout simulation results. The filter has a noise figure of 8.6-8.9 dB across 24-29 GHz and it achieves an input- referred IP3 of -1.14 dBm.

In this article, a synthesis methodology for analog circuit design is presented. This methodology utilizes symbolic math tools to systematically and exhaustively search for candidate analog circuits avoiding tedious manual work. The two-port network matrix representation of active devices, such as MOS transistors, paves the way for efficiently using advanced symbolic math toolboxes (e.g., in MAPLE or MATLAB) to automate the generation of new analog circuits and further investigate the effects of nonidealities and parasitics. Using this synthesis methodology new amplifiers, filters, and oscillators can be obtained starting from a predefined structure. This article aims to motivate and provide an overview of the current status of research in this area. In addition, two detailed design examples of a family of differential filters and a family of differential oscillators along with their simulations and measurement results are provided to illustrate and verify the synthesis methodology.

In this paper, the generation of fully differential 2ndorder voltage-mode allpass filters is systematically studied and modeled using two-port network techniques. The proposed filters are based only on the generic two transistor common-drain differential pair and a series of surrounding RLC impedances. Five designs of possible allpass filters based on various choices of the surrounding impedances are also presented. Selected designs were verified with experimental results using discrete MOS transistors as proof of concept. One of the proposed filters was simulated in 65-nm CMOS and showed 46GHz delay-bandwidth while the delay can be electronically tuned via the bias current and independent from the pole frequency.