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Inpyo Bae

dblp:207/7232 · DBLP profile ↗
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5ranked-venue papers
1as first author
0since 2021 · last 2019
0000-0002-7967-749XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 67% Reconfigurable computing and FPGAs · 33%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization › autotuning
compiler autotuning
0.312018
Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Hardware accelerators and domain-specific architectures › machine learning accelerator › CNN accelerator
CNN mapping
0.312018
Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Reconfigurable computing and FPGAs
coarse-grained reconfigurable architecture
0.312018
Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.312018
Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018

Methods — techniques the papers use, named apart from their topics

modulo scheduling · 0.7auto-tuning · 0.7
YearPublicationVenuePosition
2019 Architectures and algorithms for on-device user customization of CNNs
Barend Harris, Inpyo Bae, Bernhard Egger 0002
Integr.2
2018 Architectures and algorithms for user customization of CNNs
abstract
In this paper we present a convolutional neural network architecture that supports user customization through incremental transfer learning. The architecture consists of a large basic inference engine and a small augmenting engine. After training the basic inference engine and augmenting engine on a large general dataset, the basic inference engine is fixed. For user customization, only the augmenting engine is re-trained on-device using a small user specific dataset provided by the user. To accelerate the training of the augmenting engine we map this to a coarsegrained reconfigurable array processor. The complete network architecture is evaluated using the Caffe framework, and a C-code equivalent network is implemented and tested on a CGRA processor. Experiments with NIST'19 and our user-specific datasets show an increase in accuracy of the system from 76.3% to 93.2% after user customization. Mapping this code to a CGRA gives us a speed up of 45x and a 49-and 3-fold reduced energy consumption over an ARMv7 processor and a 3-way VLIW processor, respectively, showing the potential of CGRAs as DNN processors.
Barend Harris, Mansureh S. Moghaddam, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger 0002, Soonhoi Ha, Kiyoung Choi
ASP-DAC4
2018 C-GOOD: C-code generation framework for optimized on-device deep learning
abstract
Executing deep learning algorithms on mobile embedded devices is challenging because embedded devices usually have tight constraints on the computational power, memory size, and energy consumption while the resource requirements of deep learning algorithms achieving high accuracy continue to increase. Thus it is typical to use an energy-efficient accelerator such as mobile GPU, DSP array, and customized neural processor chip. Moreover, new deep learning algorithms that aim to balance accuracy, speed, and resource requirements are developed on a deep learning framework such as Caffe[16] and Tensorflow[1] that is assumed to run directly on the target hardware. However, embedded devices may not be able to run those frameworks directly due to hardware limitations or missing OS support. To overcome this difficulty, we develop a deep learning software framework that generates a C code that can be run on any devices. The framework is facilitated with various options for software optimization that can be performed according to the optimization methodology proposed in this paper. Another benefit is that it can generate various styles of C code, tailored for a specific compiler or the accelerator architecture. Experiments on three platforms, NVIDIA Jetson TX2[23], Odroid XU4[10], and SRP (Samsung Reconfigurable Processor)[32], demonstrate the potential of the proposed approach.
Duseok Kang, Euiseok Kim, Inpyo Bae, Bernhard Egger 0002, Soonhoi Ha
ICCAD3
2018 Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators
abstract
As more and more deep learning tasks are pushed to mobile devices, accelerators for running these networks efficiently gain in importance. We show a that an existing class of general purpose accelerators, modulo-scheduled coarse-grained reconfigurable array (CGRA) processors typically used to accelerate multimedia workloads, can be a viable alternative to dedicated deep neural network processing hardware. To this end, an auto-tuning compiler is presented that maps convolutional neural networks (CNNs) efficiently on such architectures. The auto-tuner analyzes the structure of the CNN and the features of the CGRA, then explores the large optimization space to generate code that allows for an efficient mapping of the network. Evaluated with various CNNs, the auto-tuned code achieves an 11-fold speedup over the initial mapping. Comparing the energy per interference, the CGRA outperforms other general-purpose accelerators and an ARMv8 processor by a significant margin.
Inpyo Bae, Barend Harris, Hyemi Min, Bernhard Egger 0002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2017 Incremental training of CNNs for user customization: work-in-progress
abstract
This paper presents a convolutional neural network architecture that supports transfer learning for user customization. The architecture consists of a large basic inference engine and a small augmenting engine. Initially, both engines are trained using a large dataset. Only the augmenting engine is tuned to the user-specific dataset. To preserve the accuracy for the original dataset, the novel concept of quality factor is proposed. The final network is evaluated with the Caffe framework, and our own implementation on a coarse-grained reconfigurable array (CGRA) processor. Experiments with MNIST, NIST'19, and our user-specific datasets show the effectiveness of the proposed approach and the potential of CGRAs as DNN processors.
Mansureh S. Moghaddam, Barend Harris, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger 0002, Soonhoi Ha, Kiyoung Choi
CASES4