Fixing bugs in hardware design code has become a challenging task due to the increasing complexity of modern circuit designs. As a result, automated program repair techniques have been proposed to synthesize patches for bugs in hardware designs and achieved promising results. However, existing techniques are still limited in synthesizing expressions for complex bugs. In this work, we explore the possibility of addressing complex bugs by proposing SREPAIR, a novel symbolic regression-based repair technique. The key novelty of SREPAIR lies in three aspects: 1) we propose a novel expression modification encoding that enables fine-grained adjustments to buggy expressions. 2) we introduce expression synthesis-based templates that allow for flexible and expressive repairs. 3) we develop a novel symbolic regression network-based synthesis algorithm that effectively synthesizes complex expressions. Experimental results on the four peer-reviewed datasets demonstrate that SREPAIR correctly fixes 56 bugs out of 112 bugs, which achieves 43.6% and 194.7% improvement over the previous state-of-the-art RTL-REPAIR (39 bugs) and CIRFIX (19 bugs). To evaluate the generalizability of SREPAIR, we further construct an augmented dataset of 282 bugs by mutating hardware designs. SREPAIR shows its better generalizability by correctly fixing 127 bugs, reaching 217.5% improvement over the best approach.

Driven by the stringent demands of Internet of Things (IoT) applications, extended battery life and robust temperature stability have become key design metrics for navigation and positioning chips. This article presents a low-power fractional-N phase-locked loop (PLL) with temperature compensation for navigation and positioning applications. The proposed PLL integrates a temperature-adaptive dual-loop Class-C voltage-controlled oscillator (VCO). Benefiting from the high current efficiency and reduced temperature sensitivity of the proposed dual-loop VCO, the PLL simultaneously achieves low-power consumption, stable frequency generation, and low-phase noise (PN) over a wide temperature range. Fabricated in a 0.13-$\mu $m CMOS process, the PLL consumes 5.6 mW from a 1.2 V supply. Measurement results over a temperature range of$- 40~^{\circ }$C to$125~^{\circ }$C demonstrate that the proposed PLL achieves an average frequency temperature coefficient (TC) of 0.72 ppm/°C. In addition, the PN variation remains below 0.3 dBc/Hz at a 100-kHz offset and 0.8 dBc/Hz at a 1-MHz offset.

Complexity of cryptographic algorithm renders verification of cryptographic hardware design vulnerable to the oracle problem. We propose Minoan: the first opensource verification framework based on Metamorphic testing for cryptographic hardware design to mitigate the oracle problem. Minoan constructs six metamorphic relationships for cryptographic hardware design verification based on domain knowledge, and further designs the time-aware metamorphic relationship satisfiability checking mechanism to strengthen the integration of metamorphic testing with cryptographic hardware. Finally, the evaluation on public datasets from OpenCores shows that Minoan achieves promising results with detecting up to ${9 8 . 0 2 \%}$ bugs.

Abstract Resource limitations make it challenging to provide all students with one of the most effective educational interventions: personalized instruction. Reinforcement learning could be a pivotal tool to decrease the development costs and enhance the effectiveness of intelligent tutoring software, that aims to provide the right support, at the right time, to a student. Here we illustrate that deep reinforcement learning can be used to provide adaptive pedagogical support to students learning about the concept of volume in a narrative storyline software. Using explainable artificial intelligence tools, we extracted interpretable insights about the pedagogical policy learned and demonstrated that the resulting policy had similar performance in a different student population. Most importantly, in both studies, the reinforcement-learning narrative system had the largest benefit for those students with the lowest initial pretest scores, suggesting the opportunity for AI to adapt and provide support for those most in need.

Verification of hardware design code is crucial for the quality assurance of hardware products. Being an indispensable part of verification, localizing bugs in the hardware design code is significant for hardware development but is often regarded as a notoriously difficult and time-consuming task. Thus, automated bug localization techniques that could assist manual debugging have attracted much attention in the hardware community. However, existing approaches are hampered by the challenge of achieving both demanding bug localization accuracy and facile automation in a single method. Simulation-based methods are fully automated but have limited localization accuracy, slice-based techniques can only give an approximate range of the presence of bugs, and spectrum-based techniques can also only yield a reference value for the likelihood that a statement is buggy. Furthermore, formula-based bug localization techniques suffer from the complexity of combinatorial explosion for automated application in industrial large-scale hardware designs. In this work, we propose Kummel, a K nowledge-a u g m ented m utation-bas e d bug loca l ization for hardware design code to address these limitations. Kummel achieves the unity of precise bug localization and full automation by utilizing the knowledge augmentation through mutation analysis. To evaluate the effectiveness of Kummel, we conduct large-scale experiments on 76 versions of 17 hardware projects by seven state-of-the-art bug localization techniques. The experimental results clearly show that Kummel is statistically more effective than baselines, e.g., our approach can improve the seven original methods by 64.48% on average under the RImp metric. It brings fresh insights of hardware bug localization to the community.

The verification of hardware design code is a critical aspect in ensuring the quality and reliability of hardware products. Finding bugs in hardware design code is important for hardware development and is frequently considered as a notoriously challenging and time-consuming activity while being an essential aspect of verification. Thus, bug localization techniques that could assist manual debugging have attracted much attention in the hardware community. However, there exists an unpredictable time span between the precise origin of a bug and its detected manifestation in prior work without costly formal verification. Locating the bug responsible for the exposed discrepancy between expected and exhibited design behavior remains a major challenge. In this work, we propose Tartan, a T ime- a ware spect r um-based bug localiza t ion with d a ta purificatio n for hardware design code to address these limitations. Tartan integrates hardware-specific timing information with the spectrum and captures the changes of executed statements when the state of the circuit changes to effectively locate bugs. Further, Tartan purifies the spectrum data from the simulation and evaluates the suspiciousness of the statements in the design to indicate the likelihood of being buggy. To evaluate the effectiveness of Tartan, we conduct large-scale experiments on 69 versions of 15 hardware projects by the state-of-the-art bug localization techniques. The experimental results clearly show that Tartan is statistically more effective than the baselines. It provides a new perspective on hardware design code bug localization and brings fresh insights to the community.

Hardware description languages (HDLs) are pivotal for the development of hardware designs. The programming courses for HDLs are also popular in both universities and online course platforms. Similar to programming assignments of software languages (SLs), these of HDLs also actively call for automated program repair (APR) techniques to provide personalized feedback for students. However, the research of APR techniques targeting HDL programming assignments is still in an early stage. Due to the significantly different programming mechanism of HDLs from SLs, the only APR technique (i.e., CirFix) targeting HDL programming assignments contributes a customized repair pipeline. However, the fundamental challenges in the design of HDL-oriented fault localization and patch generation still remain unresolved. In this work, we propose a signal value transition-guided defect repair technique named STRIDER by capturing the intrinsic features of HDLs. This technique consists of a time-aware dynamic defect localization approach to precisely localize defects, and a signal value transition-guided patch synthesis approach to effectively generate fixes.We further construct a dataset of 57 real defects from HDL programming assignments for tool evaluation. The evaluation reveals the overfitting issue of the pioneering tool CirFix and the significant improvement of STRIDER over CirFix in terms of both effectiveness and efficiency. In particular, STRIDER is more effective by correctly fixing 2.3X as many defects as CirFix in the real defect dataset, and is 23X more efficient by generating a correct fix within five minutes on average in the synthetic defect dataset, while CirFix takes around two hours on average.

Coverage guided dynamic verification is a widely used verification technique for RTL designs described using domain-specific languages for hardware and representing in some intermediate representations. Although the embedding of fuzz testing promote the abilities of coverage guided dynamic verification, there are lack of efficiently metric feedbacks utilization. In this paper, we proposed MMFuzz, a novel fuzzing tool enhanced by metric feedbacks. The proposed method utilze metric feedbacks efficiently in two aspects: seeds selection and mutators selection. The experimental results on several practical designs show that our method is able to achieve up to 1.0x improvements over the state-of-the-art RTL fuzzing tool with the same times of mutation.

Mutation testing, a well-suited technology for functional validation, is regrettably poorly studied in hardware. We propose Mantra: the first open-source code-level mutation testing tool based on real hardware bugs. Specifically, Mantra devises time-aware mutation killing mechanism for cost reduction of hardware mutation testing using the parallelism of hardware design code, and then defines and implements 19 hardware mutation operators via large-scale empirical analysis on real bugs. Finally, the evaluation on public datasets from CirFix and OpenCores shows that Mantra achieves promising results with a maximum boost of 83.44%.

In modern cyber-physical systems, the vast interconnected processes generated from sensor networks necessitate advanced modeling techniques to exploit decentralized data considering edge computation and data access issues. As sensors emit correlated real-life time series, successful forecasting hinges on revealing the spatio-temporal structures and qualities of data. Matrix Estimation-based (ME) methods, as state-of-the-art techniques, excel at denoising and forecasting high-dimensional correlated time series by representing spatio-temporal data as a temporal matrix. However, ME methods face challenges in handling the decentralized data and access restrictions, due to existing licensing agreements and the inherent burden of centralized modeling. To address this limitation, we propose the Federated Multivariate Singular Spectrum Analysis (Fed-mSSA), a federated matrix estimation-based framework, to denoise and predict correlated time series in the presence of noisy and decentralized data. Specifically, we introduce a novel consensus optimization problem to jointly learn the low-rank matrix representation, capturing spatio-temporal patterns to recover latent states and missing data. Furthermore, we present a federated prediction method that privately and efficiently extracts non-linear temporal dynamics using the denoised temporal matrix. Our results show that our proposed framework achieves state-of-the-art prediction performance in a distributed setting, particularly in the presence of missing data

In the era of Internet of Things (IoT), network-wide anomaly detection is a crucial part of monitoring IoT networks due to the inherent security vulnerabilities of most IoT devices. Principal Components Analysis (PCA) has been proposed to separate network traffics into two disjoint subspaces corresponding to normal and malicious behaviors for anomaly detection. However, the privacy concerns and limitations of devices’ computing resources compromise the practical effectiveness of PCA. We propose a federated PCA learning using Grassmann manifold optimization, which coordinates IoT devices to aggregate a joint profile of normal network behaviors for anomaly detection. First, we introduce a privacy-preserving federated PCA framework to simultaneously capture the profile of various IoT devices’ traffic. Then, we investigate the alternating direction method of multipliers gradient-based learning on the Grassmann manifold to guarantee fast training and low detecting latency with limited computational resources. Finally, we show that the computational complexity of the Grassmann manifold-based algorithm is satisfactory for hardware-constrained IoT devices. Empirical results on the NSL-KDD dataset demonstrate that our method outperforms baseline approaches.

Automated program repair (APR) is being leveraged in hardware description languages (HDLs) to fix hardware bugs without human involvement. Most existing APR techniques search for donor code (i.e., code fragment for bug fixing) in the original program to generate repairs, which is based on the assumption that donor code can be found in existing source code. The redundancy assumption is the fundamental basis of most APR techniques, which has been widely studied in software by searching code clones of donor code. However, despite a large body of work on code clone detection, researchers have focused almost exclusively on repositories in traditional programming languages, such as C/C++ and Java, while few studies have been done on detecting code clones in HDLs. Furthermore, little attention has been paid on the repetitiveness of bug fixes in hardware designs, which limits automatic repair targeting HDLs. To validate the redundancy assumption for HDL, we perform an empirical study on code clones of real-world bug fixes in Verilog. On top of empirical results, we find that 17.71% of newly introduced code in bug fixes can be found from the clone pairs of buggy code in the original program, and 11.77% can be found in the file itself. The findings not only validate the assumption but also provides helpful insights for the design of APR targeting HDLs.

Verification of hardware design code is crucial for the quality assurance of hardware products. As an indispensable part of verification, localizing faults in the hardware design code is significant for hardware development but is often regarded as a notoriously difficult and time-consuming task. Thus, automated fault localization techniques that could assist manual debugging have attracted much attention in the hardware community. Prior work indicates that existing methods neither fully utilize program dynamic execution information nor lack attention to timing. In this work, we propose Tarsel: a time-aware spectrum-based fault localization approach to help bridge this gap. Tarsel integrates hardware-specific timing information with the program spectrum and captures the changes of executed statements when the state of the hardware program changes to effectively locate faults. The experimental results show that Tarsel successfully locates over half of bugs in the benchmark at Top-3 and about 90% of bugs at Top-5. In addition, Tarsel statistically outperforms the state-of-the-art fault localization approach CirFix under all six typical metrics. In particular, while no bugs are ranked at Top-1 by CirFix, Tarsel successfully locates 11.41% of bugs at Top-1. It brings fresh insights of hardware bug localization to the community.

Automated program repair (APR) holds the promise of aiding manual debugging activities. Over a decade of evolution, a broad range of APR techniques have been proposed and evaluated on a set of real-world bug datasets. However, while more and more bugs have been correctly fixed, we observe that the growth of newly fixed bugs by APR techniques has hit a bottleneck in recent years. In this work, we explore the possibility of addressing complicated bugs by proposing TransplantFix, a novel APR technique that leverages graph differencing-based transplantation from the donor method. The key novelty of TransplantFix lies in three aspects: 1) we propose to use a graph-based differencing algorithm to distill semantic fix actions from the donor method; 2) we devise an inheritance-hierarchy-aware code search approach to identify donor methods with similar functionality; 3) we present a namespace transfer approach to effectively adapt donor code.

Various recurrent neural network (RNN) architectures have been implemented successfully for time series prediction in recent years.However, real-world time series data usually contain noise, which decreases the performance of the neural networks.Despite the substantial efforts to understand the pattern of time series, there is a lack of research on detecting and filtering out the inherent noise when predicting time series based on training RNN models.We propose a dual RNN strategy, namely Robust Dual Recurrent Neural Networks (RDRNN), for noisy time series prediction.We designed and trained two RNNs simultaneously and used the loss value to classify different samples into noise-free samples and noisy samples.We exchanged the small-loss samples (which were likely to be noise-free data) to fit the main pattern of time series data, and re-weighted the large-loss samples (which were likely to be noisy data) to alleviate the impact of noise.Empirical results on three popular Chinese stock market indexes demonstrate that the new learning paradigm significantly outperforms baseline approaches.Our code is available at https://jiayuheusyd.github.io/

A key challenge in education is effectively engaging children in learning activities. We investigated how a narrative story impacts engagement and learning, as well as how feedback can provide further benefits. To do so, we created an interactive, tablet-based learning platform with a multi-step math task designed using Common Core State Standards. Subjects completed a pretest and then were assigned to a condition, either one of three variations of the system (narratives, narratives with hints, and narratives with a tutoring chatbot using wizard-of-oz techniques) or a control system that has children complete the same learning task without narratives nor feedback, before the subjects completed a post test. 72 children in U.S. grades 3--5 participated. Our results showed that embedding learning activities into narratives boosted children's engagement as evaluated by coding video responses and surveys, and the integration of a tutoring chatbot improved learning outcomes on the assessment. These results provide evidence that a narrative-based tutoring system with chatbot-mediated help may support effective learning experiences for children.

Effective note-taking strategies can benefit learners over a lifetime. Studies have shown that students who take notes by hand learn more than those who take notes on a laptop. Additionally, adding drawings to notes to represent concepts and relationships significantly effects memory and learning. This practice of representing ideas through diagrams and drawings in notes is referred to as visual note-taking. To engage learners in taking handwritten visual notes, we developed VisualNote: (1) a toolkit that facilitates purposeful practice of visual note-taking, and (2) a tangible tagging process that allows for online storage of notes and sharing within class and amongst broader communities. Guided by Universal Design for Learning (UDL), we took a constructivist approach to provide alternative approaches of expression, representation, and engagement that can be leveraged to equip learners with tools to pursue more pathways to learn and make learning visible.