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Mary K. Hibbs-Brenner

dblp:208/5566 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Interconnection networks and networks-on-chip · 90% Integrated circuit design · 10%
Computer networks
1 paper
Optical networks · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Optical networks
optical interconnect
0.012000
Fully embedded board-level guided-wave optoelectronic interconnects · Proc. IEEE 2000
Interconnection networks and networks-on-chip › optical interconnection networks
free-space optical interconnects
0.012000
Smart-pixel array technology for free-space optical interconnects · Proc. IEEE 2000
Interconnection networks and networks-on-chip
optical interconnection networks
0.012000
Smart-pixel array technology for free-space optical interconnects · Proc. IEEE 2000
Interconnection networks and networks-on-chip
high-speed interconnect
0.012000
Fully embedded board-level guided-wave optoelectronic interconnects · Proc. IEEE 2000
Integrated circuit design
optoelectronic integrated circuits
0.012000
Smart-pixel array technology for free-space optical interconnects · Proc. IEEE 2000
Interconnection networks and networks-on-chip › optical interconnection networks
optoelectronic interconnection network
0.012000
Fully embedded board-level guided-wave optoelectronic interconnects · Proc. IEEE 2000

Methods — techniques the papers use, named apart from their topics

waveguide fabrication · 0.1total internal reflection mirrors · 0.1grating couplers · 0.1
YearPublicationVenuePosition
2000 Fully embedded board-level guided-wave optoelectronic interconnects
abstract
A fully embedded board-level guided-wave optical interconnection is presented to solve the packaging compatibility problem. All elements involved in providing high-speed optical communications within one board are demonstrated. Experimental results on a 12-channel linear array of thin-film polyimide waveguides, vertical-cavity surface-emitting lasers (VCSELs) (42 /spl mu/m), and silicon MSM photodetectors (10 /spl mu/m) suitable for a fully embedded implementation are provided. Two types of waveguide couplers, titled gratings and 45/spl deg/ total internal reflection mirrors, are fabricated within the polyimide waveguides. Thirty-five to near 100% coupling efficiencies are experimentally confirmed. By doing so, all the real estate of the PC board surface are occupied by electronics, and therefore one only observes the performance enhancement due to the employment of optical interconnection but does not worry about the interface problem between electronic and optoelectronic components unlike conventional approaches. A high speed 1-48 optical clock signal distribution network for Cray T-90 super computer is demonstrated. A waveguide propagation loss of 0.21 dB/cm at 850 nm was experimentally confirmed for the 1-48 clock signal distribution and for point-to-point interconnects. The feasibility of using polyimide as the interlayer dielectric material to form hybrid three-dimensional interconnects is also demonstrated. Finally, a waveguide bus architecture is presented, which provides a realistic bidirectional broadcasting transmission of optical signals. Such a structure is equivalent to such IEEE standard bus protocols as VME bus and FutureBus.
Ray T. Chen, Chulchae Choi, Yujie J. Liu, Bipin Bihari, Suning Tang, R. Wickman, B. Picor, Mary K. Hibbs-Brenner, J. Bristow, Y. S. Liu
Proc. IEEE10
2000 Smart-pixel array technology for free-space optical interconnects
abstract
This paper describes a smart-pixel array technology that is being developed at Honeywell for use in chip-to-chip optical interconnections based on free-space optics. The technology combines large-scale, two-dimensional arrays of optoelectronic and microoptical elements with VLSI electronics to enable high-density, high-speed interchip input/output capability in the optical domain. We have demonstrated prototype modules with 16/spl times/16 and 32/spl times/32 emitter and interleaved detector arrays.
E. M. Strzelecka, J. Nohava, Mary K. Hibbs-Brenner, Elias Towe
Proc. IEEE4