Carbon nanotube field effect transistors (CNFETs) are expected to replace silicon-based metal oxide semiconductor field effect transistors (MOSFETs) to improve the power efficiency and performance of microprocessors. However, the design of CNFET processors is not as mature as that of silicon-based processors because there is no architecture-level analytical tool for CNFET processors. Since circuit-level analysis such as RTL analysis is a very time-consuming and troublesome task, architecture-level analysis is needed for the rapid design of processors optimized for CNFETs.

In this paper, we design an NS3-based protocol-level simulator for the Low Earth Orbit (LEO) satellite network performance evaluation. Our simulator can provide a full-stack LEO network performance evaluation including routing, MAC, and PHY for both satellite-ground and satellite-gateway transmission. Particularly, for the PHY layer, with special focus on the multi-beam transmission of the LEO network, our designed simulator can provide multi-beam support in the satellite PHY and channel. Using our LEO satellite network simulator, we also design and implement a Multi-Frequency Time-Division Multiple Access (MF-TDMA) and contention hybrid MAC for data and control information delivery for satellite-ground and satellite-gateway. Our designed MAC can support network scanning, association, authentication, timing offset compensation, and resource scheduling, and is specially optimized to reduce the delay. Using our full-stack simulator, we evaluate the end-to-end throughput, delay, and packet loss performance combining with a time-slot shortest path routing, and this demonstrates that our designed simulator can provide fair full-stack performance evaluation for LEO network design.

In this paper, we propose CNFET7, the first open-source cell library for 7-nm carbon nanotube field-effect transistor (CNFET) technology. CNFET7 is based on an open-source CNFET SPICE model called VS-CNFET, and various model parameters such as the channel width and carbon nanotube diameter are carefully tuned to mimic the predictive 7-nm CNFET technology presented in a published paper. Some nondisclosure parameters, such as the cell size and pin layout, are derived from those of the NanGate 15-nm open-source cell library in the same way as for an open-source framework for CNFET circuit design. CNFET7 includes two types of delay model (i.e., the composite current source and nonlinear delay model), each having 56 cells, such as INV_X1 and BUF_X1. CNFET7 supports both logic synthesis and timing-driven place and route in the Cadence design flow. Our experimental results for several synthesized circuits show that CNFET7 has reductions of up to 96%, 62% and 82% in dynamic and static power consumption and critical-path delay, respectively, when compared with ASAP7.

Convolutional neural networks (CNNs) have demonstrated significant potential across a range of applications due to their superior accuracy. Edge inference, in which inference is performed locally in embedded systems with limited power resources, is researched for its energy efficiency. An approximate encoder is proposed in this study for decreasing switching activity, which minimizes power consumption in CNN accelerators at the edge. The proposed encoder performs approximate encoding based on a pattern matching of a comparison pattern and current data. Software determines the value of the comparison pattern and the availability of the recommended encoder. Experiments with a CIFAR-10 dataset utilizing LeNet5 show that using the suggested encoder, depending upon the comparison pattern, power consumption of a CNN accelerator can be reduced by 21.5% with 1.59% degradation on inference quality.

Recently emerging applications, such as convolution neural networks (CNNs), which process thousands of convolutional computations, require a large amount of power. Multiplication is the key arithmetic in these applications and an approximate multiplier has the potential to reduce both power and area. In this study, first, we propose the approximate and, then, the accurate compression method for an 8-bit multiplier. The proposed compression method single handedly reduces eight rows of partial products into three and, then, thoroughly processes the rows into two. Comparison of the conventional Wallace tree multiplier demonstrates that the proposed approximate multiplier with the compression reduces power and area by 73.7% and 60.3%, respectively. In addition, compared with two existing low-power approximate multipliers, the proposed multiplier achieves higher reductions than these state-of-the-art multipliers relative to power, area, and delay, with undegraded accuracy. These improvements can be also found from the results of a popular CNN application.

Multiplication is a key fundamental function for many error-tolerant applications. Approximate multiplication is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes an accuracy-controllable multiplier whose final product is generated by a carry-maskable adder. The proposed scheme can dynamically select the length of the carry propagation to satisfy the accuracy requirements flexibly. The partial product tree of the multiplier is approximated by the proposed tree compressor. An 8×8 multiplier design is implemented by employing the carry-maskable adder and the compressor. Compared with a conventional Wallace tree multiplier, the proposed multiplier reduced power consumption by between 47.3% and 56.2% and critical path delay by between 29.9% and 60.5%, depending on the required accuracy. Its silicon area was also 44.6% smaller. In addition, results from an image processing application demonstrate that the quality of the processed images can be controlled by the proposed multiplier design.

Approximate computing is an efficient approach for error-tolerant applications because it can trade off accuracy for power. Addition is a key fundamental function for these applications. In this paper, we proposed a low-power yet high-speed accuracy-configurable adder that also maintains a small design area. The proposed adder is based on the conventional carry look-ahead adder, and its configurability of accuracy is realized by masking the carry propagation at runtime. Compared with the conventional carry look-ahead adder, with only 14.5% area overhead, the proposed 16-bit adder reduced power consumption by 42.7%, and critical path delay by 56.9% most according to the accuracy configuration settings, respectively. Furthermore, compared with other previously studied adders, the experimental results demonstrate that the proposed adder achieved the original purpose of optimizing both power and speed simultaneously without reducing the accuracy.

Many applications, such as image signal processing, has an inherent tolerance for insignificant inaccuracies. Multipliers are key arithmetic functions for many error-tolerant applications. Approximate multipliers are considered an efficient technique to trade off energy relative to performance and accuracy. We propose two approximate multiplier designs that demonstrate lower power consumption and shorter critical path delay than the conventional multiplier by employing an approximate tree compressor. The proposed compressor halves the height of the partial product tree and generates a vector to recover accuracy. Compared to the conventional Wallace tree multiplier, one of the proposed 8-bit approximate multipliers reduces power consumption and critical path delay by 59.9% and 36.3%, respectively. Furthermore, with 0.28% normalized mean error distance, the silicon area required to implement the multiplier is reduced by 50.1%. The proposed approximate multiplier designs outperform previous multipliers relative to power consumption, critical path delay, and design area.