Green networking in the Internet becomes increasingly important. In a high-performance router, the dominant power consumer on the Internet, half of its total power usage goes into the line-cards, where the traffic managers inside consume most of it. In this paper, we propose an energy-efficient design on the traffic manager architecture for packet buffering and storage. Unlike traditional routers where packets are always kept in off-chip memory, we propose a dynamic on-chip and off-chip scheduling mechanism, called Dynamic Packet Manager (DPM), to reduce both peak and average power consumption caused by the traffic manager. DPM buffers packets in a small on-chip memory in the light-traffic period, and activates the off-chip memory on when the on-chip memory is to overflow. In this design, when the traffic is light, the off-chip memory is put into power saving state by clock gating so that the average power consumption is reduced. With an on-chip flow based and off-chip class-based design, DPM can save one off-chip memory otherwise used for the per-flow index information storage, therefore further reduce the peak power usage. We present the theoretic analysis guiding the implementation of the DPM mechanism. Experiments on three prototypes implemented on different hardware show that the peak and average power consumptions can be reduced by 27.9% and 37.5% respectively, along with less on-chip memory cost. Besides, the traffic manger with DPM shows better performance on average packet scheduling delay than the one without DPM.

Per-flow queuing is believed to be an effective approach to guarantee Quality of Service (QoS) in high performance routers. However, its brute-force implementation consumes a huge amount of memory and is not scalable as the number of flows increases. Dynamic Queue Sharing (DQS) mechanism, in which a physical queue is dynamically created on-demand when a new flow comes and released when the flow temporarily paused, is able to achieve per-flow queuing performance with much less memory. In this paper, based on DQS, an active per-flow queuing system is designed, implemented and tested. To evaluate the effectiveness of DQS, we implement two FPGA-based Traffic Manager (TM) prototypes, one with DQS and the other a traditional one. The real chip implementation shows that DQS can not only scale down the required memory for per-flow queuing but also reduce the total number of control logic elements. As a result of reduced control logic, original 3-stage scheduling in naive scheme can be improved to be a single stage while maintaining the same delay performance, thus resulting in a faster speed potential. Besides, the power consumption can also considerably be reduced. Our experiments on a 4Gbps TM prototype using Stratix EP1S80F1508C5 FPGA show a 58.6% decrease in control memory. Meanwhile, the logic cells and LC registers are reduced by 6.8% and 15.0% respectively, and the power consumption is saved by 23% compared with the brute-force per-flow queuing implementation with 8K queues.