Large Language Models (LLMs) remain vulnerable to jailbreak attacks, which attempt to elicit harmful responses from LLMs.The evolving nature and diversity of these attacks pose many challenges for defense systems, including (1) adaptation to counter emerging attack strategies without costly retraining, and (2) control of the trade-off between safety and utility.To address these challenges, we propose Retrieval-Augmented Defense (RAD), a novel framework for jailbreak detection that incorporates a database of known attack examples into Retrieval-Augmented Generation, which is used to infer the underlying, malicious user query and jailbreak strategy used to attack the system.RAD enables training-free updates for newly discovered jailbreak strategies and provides a mechanism to balance safety and utility.Experiments on StrongREJECT show that RAD substantially reduces the effectiveness of strong jailbreak attacks such as PAP and PAIR while maintaining low rejection rates for benign queries.We propose a novel evaluation scheme and show that RAD achieves a robust safety-utility trade-off across a range of operating points in a controllable manner. 1 This paper contains harmful jailbreak contents for demonstration purposes that can be offensive.

Hateful memes have become a significant concern on the Internet, necessitating robust automated detection systems. While Large Multimodal Models (LMMs) have shown promise in hateful meme detection, they face notable challenges like sub-optimal performance and limited out-of-domain generalization capabilities. Recent studies further reveal the limitations of both supervised fine-tuning (SFT) and in-context learning when applied to LMMs in this setting. To address these issues, we propose a robust adaptation framework for hateful meme detection that enhances in-domain accuracy and cross-domain generalization while preserving the general vision-language capabilities of LMMs. Analysis reveals that our approach achieves improved robustness under adversarial attacks compared to SFT models. Experiments on six meme classification datasets show that our approach achieves state-of-the-art performance, outperforming larger agentic systems.Moreover, our method generates higher-quality rationales for explaining hateful content compared to standard SFT, enhancing model interpretability. Code available at https://github.com/JingbiaoMei/RGCL

This paper presents a sub-harmonic injection-locked sub-sampling PLL (SIL-SSPLL) that realizes a peaking-free jitter transfer. The use of an injection-locked oscillator (ILO) in SSPLL allows the PLL open-loop transfer function to achieve a higher phase margin, thereby enhancing the jitter performance. The study also analyzes the effects of injection locking strength on noise rejection for both the reference signal and the VCO showing that optimal jitter performance can be achieved by properly setting the injection strength. A 13.6 to 17.7 GHz SIL-SSPLL prototype fabricated in a 40 nm CMOS technology demonstrates 74 fs RMS integrated jitter at 15.8 GHz while consuming 22.6 mW of power, leading to an excellent figure of merit (FoM) of -249.1 dBc/Hz.

WiFi passive positioning enables precise target tracking without additional devices, offering a cost-effective solution for elder care, security, and smart homes. However, it faces challenges such as distinguishing stationary humans from static objects and limited angular resolution due to existing hardware constraints. In this paper, we present WiVir, a virtual antenna array system based on commodity WiFi device for passive localization of stationary humans. The system addresses the challenges of channel state information (CSI) measurement errors and innovatively applies the concept of virtual antenna array (VAA) in WiFi-MIMO modes. It overcomes the limitation of the number of antennas in commercial WiFi Network Interface Controller (NIC) and significantly reduces the beam width of beamforming. Beamforming is used to obtain the angle of arrival (AOA), and the beam is analyzed in the frequency domain to generate a two-dimensional angular frequency image. Experimental results show that WiVir achieves 98.4% accuracy and strong robustness in indoor environments, providing precise positioning within a certain angle range.

Although quadrature digital transmitters (DTXs) are particularly useful in wideband scenarios, the interaction between I and Q paths would lead to a non-negligible distortion. Unfortunately, traditional DPD models have not performed well in solving this kind of distortion. For example, memory polynomial (MP) model uses signal amplitude as the fundamental term which is not accurate enough to solve this issue, while 2-D lookup table (2D-LUT) model requires a large number of entries which leads to significant hardware resource consumption. In view of this, we propose an area-efficient dual-path piecewise memory-polynomial (DPP-MP) model, which improves model accuracy while reducing hardware resource consumption. To further reduce the area cost, the model is pruned to 8 terms only and 4 of them are reused. To reduce the logic delay, a new squared multiplier is proposed to replace the default one, which reduces delay by 13.51% and power consumption by 2.56%. This model achieves 36.86% and 66.98% area optimization compared to MP and 2D-LUT, respectively. When applied to a 9-bit quadrature DTX with a 40 MHz 256-QAM signal, this model improves the error vector magnitude (EVM) from -16.38 dB to -35.89 dB with a target average power (Pavg) of 21.07 dBm.

A parallel acceleration strategy and hardware implementation scheme for SAR imaging is proposed to accelerate imaging in high bandwidth, large aperture, and high-density scenarios. Based on traditional SAR imaging, this strategy divides the target image into multiple local images, selecting appropriate radar data within a suitable aperture range based on the locations of each local component. Multiple SAR imaging units operate in parallel, and the local images are stitched together in their original locations to achieve accelerated imaging after cropping. This paper designs the hardware for the SAR imaging units, with its core FFT operations designed as a low-cost reusable structure. By reusing and expanding this hardware unit, the acceleration system can be built with relatively low hardware resources and minimal loss in imaging quality, demonstrating significant application potential for THz radar imaging and high-resolution large-aperture security inspections.

Time-domain signals are typically transformed using a 2D-FFT to generate the Range Doppler Map (RDM) in FMCW radar data processing. Subsequently, 2D-CFAR is applied to the RDM for target detection, while Direction of Arrival (DOA) estimation is utilized to obtain the angular information of the target, thus enabling the acquisition of the target’s spatial information. As the demand for accurate target information increases, the volume of data in each RDM frame also increases. This escalation necessitates significant hardware resources and an area to store the RDM in on-chip SRAM or a large bandwidth to accommodate it in off-chip DDRs. Furthermore, DDR controllers require substantial on-chip resources. To address this challenge, we propose a compression algorithm named APFG, which comprises Amplitude-Phase Transformation (APT), Fix-to-Float (Fix2Float), and Exponential Sharing (ESH). Experimental results demonstrate that this algorithm is applicable across various scenarios, CFAR types, and CFAR configurations, achieving high compression ratios while ensuring the accuracy of CFAR and DOA estimates. Specifically, it achieves a compression ratio of less than 14% when Pceis below 1% and a compression ratio of nearly 30% when Pdeis around 2%.

This paper proposes a quad-core, quad-mode millimeter-wave (mmWave) voltage-controlled oscillator (VCO) utilizing electromagnetic hybrid coupling. This design achieves a wide frequency tuning range and low phase noise, fulfilling the needs of integrated sensing and communication (ISAC) systems. The oscillator addresses the challenge of concurrent oscillations in multi-mode switching oscillators by implementing a switched transconductance network. The VCO also employs a controllable tail transistor array to suppress flicker noise up-conversion across a wide bandwidth, effectively reducing the 1/f3corner frequency and enhancing the phase noise performance. The VCO is fabricated in a 55-nm CMOS process occupying a core area of 0.08 mm2. Measurement results show that the VCO achieves a tuning range of 51.9% spanning from 18.7 to 31.8 GHz, and a phase noise of -110.0 dBc/Hz at 1 MHz offset while consuming 8.4 mW of power, leading to a figure of merit (FoM) of 186.2 dBc/Hz and FoMTof 200.5 dBc/Hz at 1 MHz offset.

This paper proposes a frequency-domain model for fast and accurate prediction of frequency modulation (FM) error in frequency-modulated continuous wave (FMCW) radar chirp generators. Obtaining FM error from the output frequency of a phase-locked loop (PLL) requires lengthy simulation times due to the simulator’s limited frequency quantization accuracy, which can result in discrepancies between simulated and actual performance. To address this issue, the feedback signal (DIV) sent to the phase-frequency detector (PFD) is employed in this study to quickly and accurately determine the FM error through spectrum analysis. During frequency sweeps, the feedback signal with a relatively constant frequency receives the modulating signal directly. To validate the effectiveness of the proposed model, a nested PLL-based frequency synthesizer operating from 24-27.52 GHz is designed in a 55-nm CMOS process. Measurement results show good agreement with those obtained from the model, with the difference between the simulated and measured root mean square (RMS) FM error being less than 22 kHz.

We derive and investigate two DPO variants that explicitly model the possibility of declaring a tie in pair-wise comparisons. We replace the Bradley-Terry model in DPO with two well-known modeling extensions, by Rao and Kupper and by Davidson, that assign probability to ties as alternatives to clear preferences. Our experiments in neural machine translation and summarization show that explicitly labeled ties can be added to the datasets for these DPO variants without the degradation in task performance that is observed when the same tied pairs are presented to DPO. We find empirically that the inclusion of ties leads to stronger regularization with respect to the reference policy as measured by KL divergence, and we see this even for DPO in its original form. We provide a theoretical explanation for this regularization effect using ideal DPO policy theory. We further show performance improvements over DPO in translation and mathematical reasoning using our DPO variants. We find it can be beneficial to include ties in preference optimization rather than simply discard them, as is done in common practice.

Large Multimodal Models (LMMs) excel in natural language and visual understanding but are challenged by exacting tasks such as Knowledge-based Visual Question Answering (KB-VQA) which involve the retrieval of relevant information from document collections to use in shaping answers to questions.We present an extensive training and evaluation framework, M2KR, for KB-VQA.M2KR contains a collection of vision and language tasks which we have incorporated into a single suite of benchmark tasks for training and evaluating general-purpose multi-modal retrievers.We use M2KR to develop PreFLMR, a pretrained version of the recently developed Finegrained Late-interaction Multi-modal Retriever (FLMR) approach to KB-VQA, and we report new state-of-the-art results across a range of tasks.We also present investigations into the scaling behaviors of PreFLMR intended to be useful in future developments in generalpurpose multi-modal retrievers.The code, demo, dataset, and pre-trained checkpoints are available at https://preflmr.github.io/.

Hateful memes have emerged as a significant concern on the Internet.Detecting hateful memes requires the system to jointly understand the visual and textual modalities.Our investigation reveals that the embedding space of existing CLIP-based systems lacks sensitivity to subtle differences in memes that are vital for correct hatefulness classification.We propose constructing a hatefulness-aware embedding space through retrieval-guided contrastive training.Our approach achieves state-of-theart performance on the HatefulMemes dataset with an AUROC of 87.0, outperforming much larger fine-tuned large multimodal models.We demonstrate a retrieval-based hateful memes detection system, which is capable of identifying hatefulness based on data unseen in training.This allows developers to update the hateful memes detection system by simply adding new examples without retraining -a desirable feature for real services in the constantly evolving landscape of hateful memes on the Internet.This paper contains content for demonstration purposes that may be disturbing for some readers.

This paper presents a hybrid transconductance ($g_{m}$) boosting technique exploiting both transformer coupling and cross-coupled PMOS pair to improve the conversion gain (CG) and noise figure (NF) of mm-wave mixers. To demonstrate the effectiveness of the proposed$g_{m}$-boosting technique, a high-gain and low-noise mixer for 5G FR2 frequency band applications is developed in a 40 nm CMOS process. Transformer-based pole splitting and derivative superposition are employed to enhance the mixer bandwidth and improve linearity. The mixer achieves a peak CG of 20.9 dB, a 30% fractional bandwidth ($f_{BW}$), a minimum NF of 7.7 dB, and an input referred 1-dB compression point of −14 dBm, leading to an excellent figure of merit (FOM) of 11.05. The mixer consumes 15.6 mW of power and occupies a die area of 0.31 mm2.

A 32 fs RMS jitter oversampling phase-locked loop (OSPLL) exploiting a high-gain cross-switching phase detector (CSPD) is proposed. The over-sampling PLL increases sam-pling frequency by 4x, reducing the in-band phase noise and overcoming the loop bandwidth limitation due to the reference frequency. Leveraging the increased loop bandwidth, the noise contribution of the voltage-controlled oscillator (VCO) is sig-nificantly suppressed. The high-gain CSPD adopts a common-mode sampling technique with time interleaving switches to ensure that the reference clock is sampled only at the maximum slew rate. The CSPD with a higher gain facilitates reducing the noise contribution from the phase detector (PD) and the transconductance cell. Additionally, an RC poly-phase filter (PPF) is employed to generate quadrature clocks, avoiding the deterioration of the PLL's low offset frequency phase noise. The PLL is implemented in a 40-nm CMOS process. Simulation results show that the PLL achieves a 32 fs RMS jitter integrated from 10 kHz to 100 MHz and a power consumption of 6.5 mW, resulting in an$FoM_{jitter}$of -261 dB. At 3.84 GHz frequency, the in-band phase noise is -136.8 dBc/Hz at 100 kHz offset.

This paper proposes a high-efficiency low-ripple dual-mode switched-capacitor (SC) DC-DC converter for low-power IoT and wearable device applications. A hybrid self-biased current scheme (HSBC) is developed to achieve low output voltage ripple and fast response. Two supply voltage domains of HSBC and clock drive controller circuit are introduced to reduce the power loss of the control circuit. An on-chip ultra-low-power bias circuit is also designed to minimize the power loss of the bias generator. The proposed DC-DC converter is implemented in a 40 nm CMOS process. Post-layout simulation results show that the converter realizes 1.6-1.8 V to 0.4 V conversion. The peak efficiency is up to 88% at$5\ \mu\mathrm{A}$, and the voltage ripple is less than 10 mV over a load range of 10 nA-$10\ \mu\mathrm{A}$. The response time of the converter is less than$15\ \mu\mathrm{s}$.

Knowledge-based Visual Question Answering (KB-VQA) requires VQA systems to utilize knowledge from external knowledge bases to answer visually-grounded questions. Retrieval-Augmented Visual Question Answering (RA-VQA), a strong framework to tackle KB-VQA, first retrieves related documents with Dense Passage Retrieval (DPR) and then uses them to answer questions. This paper proposes Fine-grained Late-interaction Multi-modal Retrieval (FLMR) which significantly improves knowledge retrieval in RA-VQA. FLMR addresses two major limitations in RA-VQA's retriever: (1) the image representations obtained via image-to-text transforms can be incomplete and inaccurate and (2) similarity scores between queries and documents are computed with one-dimensional embeddings, which can be insensitive to finer-grained similarities. FLMR overcomes these limitations by obtaining image representations that complement those from the image-to-text transform using a vision model aligned with an existing text-based retriever through a simple alignment network. FLMR also encodes images and questions using multi-dimensional embeddings to capture finer-grained similarities between queries and documents. FLMR significantly improves the original RA-VQA retriever's PRRecall@5 by approximately 8\%. Finally, we equipped RA-VQA with two state-of-the-art large multi-modal/language models to achieve $\sim62$% VQA score in the OK-VQA dataset.

Alexandru Coca, Bo-Hsiang Tseng, Jinghong Chen, Weizhe Lin, Weixuan Zhang, Tisha Anders, Bill Byrne. Proceedings of the 24th Annual Meeting of the Special Interest Group on Discourse and Dialogue. 2023.

Behavior sequences are generated by a series of spatio-temporal interactions and have a high-dimensional nonlinear manifold structure. Therefore, it is difficult to learn 3D behavior representations without relying on supervised signals. To this end, self-supervised learning methods can be used to explore the rich information contained in the data itself. Context-context contrastive self-supervised methods construct the manifold embedded in Euclidean space by learning the distance relationship between data, and find the geometric distribution of data. However, traditional Euclidean space is difficult to express context joint features. In order to obtain an effective global representation from the relationship between data under unlabeled conditions, this paper adopts contrastive learning to compare global feature, and proposes a self-supervised learning method based on hyperbolic embedding to mine the nonlinear relationship of behavior trajectories. This method adopts the framework of discarding negative samples, which overcomes the shortcomings of the paradigm based on positive and negative samples that pull similar data away in the feature space. Meanwhile, the output of the network is embedded in a hyperbolic space, and a multi-layer perceptron is added to convert the entire module into a homotopic mapping by using the geometric properties of operations in the hyperbolic space, so as to obtain homotopy invariant knowledge. The proposed method combines the geometric properties of hyperbolic manifolds and the equivariance of homotopy groups to promote better supervised signals for the network, which improves the performance of unsupervised learning.

This paper proposed a cascaded harmonic enhanced injection-locked frequency tripler fabricated in a 40-nm CMOS process. In order to suppress the fundamental signal and the second harmonic signal, an injection-locked doubler is explored, and then the obtained ×2 frequency signal is mixed with the fundamental signal to realize the third harmonic signal and then the third harmonic signal is injected into the tank of the injection-locked frequency selection network to improve the output power. The tripler achieves a fundamental suppression over -69 dBc and a second harmonic suppression over -66 dBc. The output power over the entire locking range from 71.5 to 86.7 GHz is larger than 5.5 dBm. The chip occupies a die area of 0.25 × 0.35mm2and dissipates 20 mW of power.

This paper presents a continuous frequency switching zig-zag voltage-controlled oscillator (VCO) to overcome the frequency discontinuity problem during the band switching process in multi-band wideband VCOs. Complementary PMOS and NMOS varactors are explored to realize opposite VCO tuning gains with high linearity. The VCO reduces the nonlinearity of the transmitted chirp in frequency-modulated continuous-wave (FMCW) radars, improving the range resolution. Implemented in a 40-nm CMOS technology, the proposed zig-zag multi-band VCO shows a simulated maximum peak frequency error of 10 MHz over 23.4-27.6 GHz frequency range, a −106.6 dBc/Hz phase noise at 1 MHz offset, and a −183.1 dBc/Hz FoM while consuming 12.69 mW power.

This paper proposes and experimentally validates a novel WiFi-based radar model for indoor WiFi sensing, which enables accurate measurement of the radial velocity of objects. A human respiratory monitoring system based on the proposed WiFi radar model is developed. The respiratory monitoring system also leverages principal component analysis (PCA) on the MIMO WiFi channel state information ratio (CSIR) information to extract the components related to human activities. Doppler frequency of respiratory motion is obtained from time-frequency analysis of the CSIR through short-time Fourier transform (STFT). Experimental results show that the WiFi-based radar model achieves high accuracy in velocity measurement with an average error of less than 1.5% and can be used to real-time monitor the respiration rate.

This article presents a 5-GS/s 6-bit flash analog-to-digital converter (ADC) in a 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The ADC jointly employs partially active second-stage comparison and$2\times $time-domain latch interpolation (TDI) to reduce power consumption and avoid extensive calibrations. To enhance the conversion speed of the second-stage structure, the stringent timing constraint is resolved by a 25%–75% duty-cycle clock scheme, a 0.5-bit redundancy in the first comparison stage, and an embedded second-stage slice selection logic. The bandwidth requirements of the track-and-hold (T/H) and T/H buffer under the 25%–75% duty-cycle clock are analyzed. An on-chip successive-approximation (SA)-based comparator offset calibration scheme utilizing FDSOI back-gate bias is also developed, providing sufficient calibration range without impairing comparator speed. The measured prototype achieves a signal-to-noise and distortion ratio (SNDR) of 32.8 dB and a spurious-free dynamic range (SFDR) of 41.82 dB at Nyquist frequency while consuming 15.07 mW power, translating into a Walden figure-of-merit (FOM) of 84.5 fJ/conversion-step.

This paper presents a wideband millimeter wave (mmW) LNA fabricated in a 55-nm CMOS process. Inter-stage transformer peak splitting and gain equalization techniques are proposed to improve bandwidth and gain flatness. A transformer- based anti-phase coupling (TBAC) method is developed to enhance effective transconductance boosting, while optimizing noise figure (NF). The LNA achieves a peak gain of 11.8 dB with a gain variation of less than ±0.8 dB, a flat gain bandwidth (FGBW) of 15 GHz (66-81 GHz) and a BW-3dB of 20 GHz (64-84 GHz). The measured NFmin is 5.09 dB at 75 GHz and the input-referred 1dB compression point (IPidB) is -5.8 dBm at 78 GHz. The LNA consumes 40 mA from 1 V power supply.

This paper presents a 6-bit 20 GS/s 2-way time-interleaved (TI) flash analog-to-digital converter (ADC) in a 28-nm FDSOI CMOS technology. Leveraging threshold voltage control via back-gate bias in FDSOI, an automatic comparator offset calibration scheme is developed, which does not require extra transistor pairs or capacitive loads in signal path, thus avoiding comparator speed degradation. To alleviate channel mismatch-induced errors in highly interleaved structure while maintaining a reasonable power efficiency, the ADC adopts a two-way TI structure with the subADC working at 10 GS/s. To further improve the ADC power efficiency, a 1-bit voltage-domain interpolation is utilized. The proposed flash ADC achieves a SNDR of 31.2 dB at Nyquist frequency with a power consumption of 204 mW, translating into a figure-of-merit (FOM) of 344 fJ/conv.-step.

This paper presents a quadrature frequency synthesizer (QFS) utilizing a switched-coupled slotted inductor (SCSI)-based voltage-controlled oscillator (VCO) to simultaneously improve the reference spurs and out-of-band phase noise while achieving a wide frequency tuning range for multiband 5G mm-Wave (mmW) applications. The QFS is implemented in a 55 nm CMOS process, achieving a reference spurs of -64 to -72 dBc, an in-band phase noise of -81.7 to -87 dBc/Hz at 100 kHz offset and an out-of-band phase noise of -119.1 to -125.4 dBc/Hz at 10 MHz offset, respectively, over the entire 19.89 to 26.35 GHz frequency locking range. The RMS jitter for a 19.89 GHz carrier is 118.7 fs, corresponding to a jitter FOM of -238.47 dB. The chip occupies a die area of 1.31 × 2.13 mm2including the testing pads and dissipates 101 mW of power.

Rapidly evolving technologies and applications of mobile devices inevitably increase the power demands on the battery. However, the development of batteries can hardly keep pace with the fast-growing demands, leading to short battery life, which becomes the top complaints from customers. In this article, we investigate a novel energy supply technology, fuel cell (FC), and leverage its advantages of providing long-term energy storage to build a hybrid FC-battery power system. Therefore, mobile device operation time is dramatically extended, and users are no longer bothered by battery recharging. We examine real-world smartphone usage data and find that a naive hybrid power system cannot meet many users’ highly diversified power demands. We thus propose an OS-level power management policy that reduces the device power consumption for each power peak to solve this mismatch. This technique trades the quality-of-service (QoS) for a larger FC ratio in the system and thus much longer device operation time. We further observe that the user’s personality largely determines his/her satisfaction with the QoS degradation and the operation time extension. Thus, applying a hybrid system with fixed configuration (i.e., peak throttling level coupled with corresponding FC/battery ratio) fails to satisfy every user. We then explore customized hybrid system configuration based on each individual user’s personality to deliver the optimal satisfaction for him/her. The experimental results show that our personality-aware hybrid FC-battery solution can achieve 4× longer operation time and 25% higher satisfaction score compared to the common setting for state-of-the-art mobile devices.

This paper presents a successive-approximation-register (SAR)-assisted time-interleaved digital-slope analog-to-digital converter (ADC), which takes advantage of both moderate conversion speed of the SAR ADC and low noise of the digital-slope ADC. A coarse SAR ADC is pipelined with 4 channels of digital-slope fine ADC through passive residue transfer for speed, precision and power optimization. A charge sharing-based implementation of the digital-slope ADC eliminates the need for power-consuming on-chip reference buffers. A compact bootstrapped switch-based chopper is proposed to minimize the hardware overhead. Designed and simulated in a 28 nm FDSOI CMOS technology, the proposed ADC achieves a SNDR of 63.74 dB at 500 MS/s while dissipating 2.4 mW, leading to a FOM of 3.83 fJ/conv.-step.

This paper presents a low-power silicon photomultiplier (SiPM) readout front-end with on-chip fast pulse generation and successive-approximation-register (SAR) ADC. The front-end mainly consists of a current buffer with an on-chip C-R high pass filter (HPF), a charge integrator, a current discriminator, and a 10-bit low-power SAR ADC. The current-mode buffer offers a low input impedance thus achieving a high input bandwidth. The on-chip HPF shortens the width of the SiPM's long-tailed single photo-electron (SPE) response to generate the fast pulse signal, which allows the current discriminator to suppress the uncertainty of timing measurement and helps to achieve a better coincidence resolving time (CRT). Compared with off-chip fast pulse generators, no additional I/O pin is required facilitating compact multi-channel SiPM readouts. By reusing the charge integration capacitor as the sampling capacitor of the SAR ADC, the power-hungry charge sensitive amplifier (CSA) is eliminated. The front-end is designed in a 0.18 μm 1P6M standard CMOS technology, and has a low power consumption of 4 mW. The on-chip HPF reshapes the long-tailed SPE pulse width from 50 ns to 3 ns. At 1 MS/s, the SAR ADC consumes 132 μW from a 1.8 V supply, and achieves a SNDR of 58.11 dB and a SFDR of 72.47 dB, respectively.

We present a low power radio frequency interference (RFI) mitigating receiver back-end application specific integrated circuit (ASIC). The ASIC includes an on-chip analog to digital converter (ADC) and a RFI detecting/mitigating digital signal processing (DSP) block. The ASIC is capable of processing signals with bandwidths exceeding 1.0GHz. The ADC has a 10-bit, 2 GS/s radiation-hard successive approximation register (SAR) architecture. The DSP block includes a 1024-channel polyphase filter bank (PFB), a fast fourier transform (FFT) blocks and Kurtosis detection & accumulation block. The total power consumed is less than 190mW, including both ADC and DSP. The DSP will have a high degree of programmability that includes the selection/bypassing of the Kurtosis estimation, selection of the number of channels, selection of the decimation factor and selection of time spans for the accumulation of statistical averages.

This paper presents a 14-bit 2.5 GS/s current-steering digital-to-analog converter (DAC) in 65 nm CMOS. Small transistors are utilized in this design to reduce the 3rd-order harmonic distortion caused by finite output impedance. However, the adoption of small transistors increases the 2nd-order harmonic distortion and degrades the spurious-free dynamic range (SFDR). Hence a digital pre-distortion (DPD) scheme is proposed for 2nd-order harmonic distortion cancellation. In addition, techniques including dynamic element matching (DEM), double-data-rate (DDR) quad switch and always-on cascode switch are employed in this design to further enhance the SFDR. Simulation results show >70 dB SFDR for input frequencies from 34 MHz to 1.2 GHz. The DAC consumes 375 mW from a dual 1.2/2.5 V power supply.

Repeatability, isolation and accuracy are the most desired factors while testing wireless devices. However, they cannot be guaranteed by traditional drive tests. Channel emulators play a major role in filling these gaps in testing. In this paper we present an efficient channel emulator which is better than existing commercial products in terms of cost, remote access, support for complex network topologies and scalability. We present the hardware and software architecture of our channel emulator and describe the experiments we conducted to evaluate its performance against a commercial channel emulator.

This paper presents a radiation-hardened-by-design digital delay locked loop (DLL) for DDR2 memory interface. The DLL utilizes thermometer coding with bubble correction and phase combination to cope with single event effects (SEEs). In addition, phase interpolation and duty cycle corrector are employed to achieve both high resolution and low duty cycle distortion. The proposed DLL is designed and simulated in a 0.13 μm CMOS technology. Simulation results show that the DLL is hardened against SEEs for charge injection as large as 250 fC and can recover quickly from radiation strikes on its sensitive nodes. The DLL operates at 267 MHz with 10% input duty cycle distortion and 30 ps delay resolution. It consumes 6.3 mW of power under 1.5 V power supply.

The automatic frequency calibration (AFC) technique is routinely used in the wideband frequency synthesizers which contain multiple voltage-controlled oscillator (VCO) tuning curves. In this paper, a counter-based AFC design method is presented. The relationship between the AFC counting time and the VCO tuning curve characteristic is quantitatively analyzed. An AFC circuit which uses a time-to-digital converter (TDC) in the counting process is developed. Simulation results show that the proposed circuit significantly reduces the AFC calibration time while preserving the calibration accuracy. The simulated error-free AFC time of the proposed AFC is less than 3 µs.

A current-mode passive mixer with conversion gain that is robust to process, supply voltage, and temperature (PVT) variations is presented. The passive mixer includes a transconductance amplifier having a source degeneration capacitor. The conversion gain of the current-mode passive mixer is proportional to the ratio of the source degeneration capacitance CSto the load capacitance CL. This technique eliminates the need for extra PVT compensation circuitry. Moreover, the conversion gain of the mixer can be designed to be programmable without relying on any gain detecting circuitry. A test chip fabricated in a 90-nm CMOS process demonstrates the PVT-robustness of the proposed mixer.

This paper presents an all-CMOS temperature sensor front-end operating at low supply voltage. The front-end includes a reference voltage generator and a proportional-to-absolute-temperature (PTAT) voltage generator. In order to minimize the errors due to various mismatches, error correction techniques including gain boosting, dynamic element matching, dynamic offset cancellation and clock boosting have been investigated. Detailed analysis and simulation have been presented. Furthermore, experimental results with 0.5 μm implementation demonstrated that the lowest supply voltage is 1.1 V for the reference voltage generator and 1 V for the PTAT voltage generator over the temperature range of -55°C to 125°C with acceptable performance for a CMOS-based temperature sensor front-end. The effectiveness of the error correction techniques are also demonstrated experimentally.

This paper presents transistor-level design of a continuous-time (CT) reconfigurable ΔΣ modulator in a 1.2 V 65 nm CMOS process. Both architectural- and circuit-level power-optimization techniques, such as flexible loop order and quantizer bit, switchable OTA unit cells, and folding flash ADC, are utilized to achieve power efficiency over all bandwidths. As gate leakage current in 65 nm technology becomes prominent, a DAC biasing scheme that is robust to gate leakage current is employed. Simulation results show that the modulator achieves signal-to-noise-and-distortion-ratio (SNDR) of 73.3/76.5/77.4/84.4 dB for 20/10/3/0.5 MHz bandwidth (BW) with power consumption of 23.9/20.7/9.49/7.22 mW, respectively. The respective figure of merit (FOM) equals 0.16/0.19/0.26/0.53 pJ/conv.

A 12-bit 60 MS/s SHA-less opamp sharing pipeline ADC utilizing switch-embedded dual-input current-reused opamp is presented in this paper. The proposed opamp sharing technique reduces the power consumption without suffering from memory effect. Two-phase overlapping clocks are proposed to ensure analog transistors in the common-mode feedback (CMFB) loop to always work in saturation thus avoiding common mode voltage settling due to the switch turn-on delay. To further reduce the power consumption, the sampling clock in the first multiplying digital-to-analog converter (MDAC) is split into two phases to reduce the gain-bandwidth (GBW) requirement of the flash ADC without sacrificing the opamp settling time. The ADC fabricated in a 0.13-μm CMOS process demonstrates a maximum SNDR of 64.9 dB and a peak SFDR of 77.1 dB at 60 MS/s. The core ADC with an active die area of 2.3 mm2consumes 36 mW of power at 60 MS/s under 1.2-V power supply.

In this paper, we apply the Arnoldi method to generate accurate reduced-order models for coupled energy domain nonlinear microelectromechanical devices. Besides the traditional application of Arnoldi method to generate reduced-order models for linear systems, we propose a new algorithm by combining the Arnoldi method and Taylor series expansion for carrying out model-order reduction on quadratic or even higher order nonlinear systems. A well-known nonlinear MEMS device, electrostatic actuated fixed-fixed beam device with squeeze-film damping effect, is studied. Simulation results demonstrate that the reduced nonlinear model has a much better accuracy to capture the original device behavior than the simple linearization method. The reduced MEMS device model can be easily connected to a circuit simulator for efficient system level simulations.