The increasing processing power of today's HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. The paper presents the CONTREX European project and its preliminary results. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels.

This paper presents how to integrate formally based models relying on the Synchronous Dataflow Model-of- Computation (MoC) in a UML/MARTE component-based application model. This model corresponds to a flexible and expressive modelling methodology, which facilitates finding and building an application model with the intended semantics, but does not help to ensure a strict fulfilment of functional and extrafunctional requirements. However, this capability has become a need in the context of modelling mixed-criticality applications. This paper shows how the component-based UML/MARTE models captured in such a flexible methodology can integrate parts transformable into synchronous data-flows. This formalism facilitates the analysis of the functional and extra-functional properties of such parts. Specifically, the paper shows a set of modelling patterns which can be translated into SDF counterparts. Relying on these patterns, a framework has been implemented which enables a bi-directional interoperability between the UML/MARTE models abiding the patterns and the formally-based ForSyDe methodology.

short-paper Share on A model-based, single-source approach to design-space exploration and synthesis of mixed-criticality systems Authors: F. Herrera Microelectronics Engineering Group, TEISA Dpt., University of Cantabria Santander, Spain Microelectronics Engineering Group, TEISA Dpt., University of Cantabria Santander, SpainView Profile , P. Peñil Microelectronics Engineering Group, TEISA Dpt., University of Cantabria Santander, Spain Microelectronics Engineering Group, TEISA Dpt., University of Cantabria Santander, SpainView Profile , E. Villar Microelectronics Engineering Group, TEISA Dpt., University of Cantabria Santander, Spain Microelectronics Engineering Group, TEISA Dpt., University of Cantabria Santander, SpainView Profile Authors Info & Claims SCOPES '15: Proceedings of the 18th International Workshop on Software and Compilers for Embedded SystemsJune 2015Pages 88–91https://doi.org/10.1145/2764967.2784777Published:01 June 2015Publication History 9citation113DownloadsMetricsTotal Citations9Total Downloads113Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Efficient design of predictable systems on top of multiprocessor-based architectures is challenging. It demands an integration effort to support system models relying on Models-of- Computation (MoC) theory, supporting real-time (RT) analysis and electronic system-level (ESL) design techniques. This paper presents a SystemC-based framework for modelling and time analysis of predictable embedded systems which aims such an integration. The framework has features for system-level design and research of predictable systems. Moreover, the framework is extensible, to enable experts from different communities to explore and assess their contributions, e.g. new schedulers, schedulability analyses, and predictable platform components, without having to rely on a physical platform.

Mixed-criticality system (MCS) design is an emerging discipline, which has been identified as a core foundational concept in fields such as cyber-physical systems. The hard real-time design community has pioneered the contributions to MCS design, extending scheduling theory to consider mixed-criticalities and the impact of on-chip and off-chip communication infrastructures. However, the development of MCS design methodologies capable to provide safe and efficient solutions for complex applications and platforms in an acceptable design time demands a more interdisciplinary approach. This paper is a first step towards such an approach in the development of MCS design methodologies. The paper first identifies main design disciplines to be involved in MCS design, both at SoC and system-of-systems (SoS) scales. Then, the paper proposes a core ontology for modelling a mixed-criticality system at both SoC scale (MCSoC) and SoS scale (MCSoS). Finally, the paper introduces a set of aspects required for MCS design which have been identified as open and challenging attending the overviewed state-of-the-art.

The consideration of an embedded device's power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of today's heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties that enables fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed flow is currently under implementation in the COMPLEX FP7 European integrated project.

This paper presents a framework which, starting from a UML/MARTE model of the embedded system, relies on an enhanced IP-XACT description of the platform for the automatic generation of fast performance executable models. The IP-XACT description of the HW architecture is automatically generated from the UML/MARTE model. The enhancement proposed extends the current capabilities of the IP-XACT standard in order to add semantic information to the HW architecture and to support the integration of Hardware Dependent Software (HdS). This way, HW and SW aspects of the integration of a component in a virtual platform model are covered. The applicability of the proposed extensions is shown by supporting the proposed IP-XACT descriptions at the front-end of a simulation infrastructure suited for fast performance assessment, and for supporting design space exploration.

This paper proposes a SystemC-based specification methodology of adaptive embedded systems to be implemented on a platform including one or more processors, thus supporting the execution of embedded software, and digital hardware with capabilities of partial dynamic reconfiguration (DRHW). For it, it proposes the collaboration of two specification methodologies: HetSC and OSSS+R. The main issues for the integration of these specification methodologies are addressed. This includes how to install and use them together, which is the structure of the specification, how adaptivity is specified for SW and DRHW implementation, and the syntactical and semanticual issues related to the MoC interface implicit in their connection.

Today's heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of these systems is still a complex and error-prone task due to the different Models of Computations (MoCs), design languages and tools associated with each of the domains. Though making such systems adaptive is technologically feasible, most of the current design methodologies do not explicitely support adaptive architectures. This paper present the ANDRES project. The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES) based on the modelling language SystemC. Using domain-specific modelling extensions and libraries, ANDRES will provide means to efficiently use and exploit adaptivity in embedded system design. The design flow is completed by a methodology tools for automatic hardware and software synthesis for adaptive architectures.

This work proposes a methodology which enables heterogeneous specification of complex, electronic systems in SystemC supporting the integration of components under different models of computation (MoCs). This feature is necessary in order to deal with the growing complexity, concurrency, and heterogeneity of electronic embedded systems. The specification methodology is based on the SystemC standard language. Nevertheless, the use of SystemC for heterogeneous system specification is not straightforward. The first problem to be addressed is the efficient and predictable mapping of untimed events required by abstract MoCs over the discrete-event MoC on which the SystemC simulation kernel is based. This mapping is essential in order to understand the simulation results provided by the SystemC model of those MoCs. The specification methodology proposes the set of rules and guidelines required by each specific MoC. Moreover, the methodology supports a smooth integration of several MoCs in the same system specification. A set of facilities is provided covering the deficiencies of the language. These facilities constitute the methodology-specific library called HetSC. The methodology and associated library have been demonstrated to be useful for the specification of complex, heterogeneous embedded systems supporting essential design tasks such as performance analysis and SW generation.

This paper presents a heterogeneous specification methodology built on top of the standard SystemC kernel. The methodology enables abstract specification supporting heterogeneity, which in this context entails the ability to describe and connect parts of the system specification under different models of computation (MoCs). A main and distinguishing contribution of the methodology is that the support is provided while maintaining the standard kernel of SystemC unchanged, by means of a set of specification rules and a heterogeneous support library built on top of the SystemC standard library. This is possible thanks to an abstraction technique that can integrate any new MoC that can be abstracted over the underlying discrete-event simulation kernel. Primitives, guidelines and rules of the specification methodology, including those related to heterogeneous support, and the basis of the abstraction technique are described. Experimental results demonstrate the benefits of the methodology.

As both the ITRS and the Medea+ DA Roadmaps have highlighted, early performance estimation is an essential step in any SoC design methodology based on International Technology Roadmap for Semiconductors (2001) and The MEDEA+ Design Automation Roadmap (2002). This paper presents a C++ library for timing estimation at system level. The library is based on a general and systematic methodology that takes as input the original SystemC source code without any modification and provides the estimation parameters by simply including the library within a usual simulation. As a consequence, the same models of computation used during system design are preserved and all simulation conditions are maintained. The method exploits the advantages of dynamic analysis, that is, easy management of unpredictable data-dependent conditions and computational efficiency compared with other alternatives (ISS or RT simulation, without the need for SW generation and compilation and HW synthesis). Results obtained on several examples show the accuracy of the method. In addition to the fundamental parameters needed for system-level design exploration, the proposed methodology allows the designer to include capture points at any place in the code. The user can process the corresponding captured events for unrestricted timing constraint verification.

In this chapter we show the ability to specify with SystemC under the restrictions imposed by several model of computations, namely CSP, KPN and SR. Specifying under these MoCs provides some important properties, specially determinism and more protection against blocking, which are also important when implementation process is faced. In most cases, standard primitive SystemC channels or a combined use of them is suitable for specifying under these MoC restrictions. Nevertheless we provide some new specific and compatible channels providing important features, as dynamic checking of restrictions or atomic use. These channels represent an extension of the standard SystemC library.