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Jeffrey A. Jacob

dblp:21/2305 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 77% Memory systems · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › reconfigurable architecture
reconfigurable processor
0.011999
Memory Interfacing and Instruction Specification for Reconfigurable Processors · FPGA 1999
Memory systems
memory consistency
0.011999
Memory Interfacing and Instruction Specification for Reconfigurable Processors · FPGA 1999

Methods — techniques the papers use, named apart from their topics

transmogrifier-2 · 0.0MIPS-like processor · 0.0
YearPublicationVenuePosition
1999 Memory Interfacing and Instruction Specification for Reconfigurable Processors
abstract
As custom computing machines evolve, it is clear that a major bottleneck is the slow interconnection architecture between the logic and memory.This paper describes the architecture of a custom computing machine that overcomes the interconnection bottleneck by closely integrating a fixed-logic processor, a reconfigurable logic array, and memory into a single chip, called OneChip-98.The OneChip-system has a seamless programming model that enables the programmer to easily specify instructions without additional complex instruction decoding hardware.As well, there is a simple scheme for mapping instructions to the corresponding programming bits.To allow the processor and the reconfigurable array to execute concurrently, the programming model utilizes a novel memory-consistency scheme implemented in the hardware.To evaluate the feasibility of the OneChip-architecture, a 32-bit MIPS-like processor and several performance enhancement applications were mapped to the Transmogrifier-2 field programmable system.For two typical applications, the 2-dimensional discrete cosine transform and the 64-tap FIR filter, we were capable of achieving a performance speedup of over 30 times that of a stand-alone state-of-the-art processor.1.
Jeffrey A. Jacob, Paul Chow
FPGA1