Analysis of an instruction set as large and varied as the one specified for the VAX-11 architecture is important for aiding processor design evaluation. This paper looks at dynamic VAX-11 instruction set usage by one class of programs, and discusses the methodology and tools which have been developed to provide that information. Six VAX/VMS native mode compilers from Digital Equipment Corporation were used: BASIC, BLISS, COBOL, FORTRAN, PASCAL, and PL/I. A summary of results generated by analyzing executions of these six compilers is presented. Information is included for instruction and class frequency, general instruction features, operand specifiers, the memory data stream, register utilization, instruction sequencing, and branch displacements.

The concept of abstract data types is extended to associate performance information with each abstract data type representation. The resulting performance abstract data type contains a functional part which describes the functional properties of the data type and a performance part which describes the performance characteristics of the data type. The performance part depends upon 1) the algorithms and data representation selected to represent the data type, 2) the particular machine on which the software realization of the data type is realized, and 3) the statistical properties of the actual data represented by the data objects involved in the data type. Methods for determining the necessary information to specify the performance part of the representation are discussed.

Performance analysis has always been considered important in computer design work. The area of central processing unit (CPU) design is no exception, where the successful development of performance evaluation tools provides valuable information in the analysis of design tradeoffs. Increasing integration of hardware is producing more complicated processor modules which add to the number of alternatives and decisions to be made in the design process. It is important that these modules work together as a balanced unit with no hidden bottlenecks. This paper describes a project to develop performance simulation as an analysis tool in CPU design. The methodology is first detailed as a three part process in which a performance simulation program is realized that executes an instruction trace using command file directions. Discussion follows on the software implemented, applications of this tool in CPU design, and future goals.

An automated software design system emphasizing dynamic performance analysis is a goal of research currently being done at the University of Connecticut. An approach for providing low level operator performance information and implementation of the software is presented. This includes an operator definition process and incorporation of defined operators into data operation modules by association with a data structure. Along with a discussion of future plans, some advantages of the approach are mentioned.