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Andrey Naraikin

dblp:21/2883 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2009
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 46% Processor architecture and microarchitecture · 23% Memory systems · 23%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation
benchmarking
0.112009
Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications · SC 2009
Performance modeling and evaluation › parallel system performance
cluster performance analysis
0.112009
Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications · SC 2009
Processor architecture and microarchitecture
multicore design
0.112009
Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications · SC 2009
Memory systems
non-uniform memory access
0.112009
Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications · SC 2009
High-performance computing
performance optimization at scale
0.012009
Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications · SC 2009

Methods — techniques the papers use, named apart from their topics

turbo boost · 0.1SMT · 0.1NAS Parallel Benchmarks · 0.1HPCC benchmarks · 0.1
YearPublicationVenuePosition
2009 Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications
abstract
In this paper, we present an early performance evaluation of a 624-core cluster based on the Intel® Xeon® Processor 5560 (code named "Nehalem-EP", and referred to as Xeon 5560 in this paper)---the third-generation quad-core architecture from Intel. This is the first processor from Intel with a non-uniform memory access (NUMA) architecture managed by on-chip integrated memory controller. It employs a point-to-point interconnect called the Intel® QuickPath Interconnect (QPI) between processors and to the input/output (I/O) hub. It also introduces to a quad-core architecture both Intel's hyper-threading technology (or simultaneous multi-threading, "SMT") and Intel® Turbo Boost Technology ("Turbo mode") that automatically allow processor cores to run faster than the base operating frequency if the processor is operating below rated power, temperature, and current specification limits. It can be engaged with any number of cores or logical processors enabled and active. We critically evaluate these features using the High Performance Computing Challenge (HPCC) benchmarks, NAS Parallel Benchmarks (NPB), and four full-scale scientific applications. We compare and contrast the results of a cluster based on the Xeon 5560 with an SGI® Altix® ICE 8200EX cluster of quad-core Intel® Xeon® 5472 Processor ("Xeon 5472" from here on) and another cluster of Intel® Xeon® 5462 Processor ("Xeon 5462"; the Xeon 5400 Series Processors are previous generation quad-core Intel processors and were code named Harpertown).
Subhash Saini, Andrey Naraikin, Rupak Biswas, David Barkai, Timothy Sandstrom
SC2