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Francois J. Bitz

dblp:21/3519 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Computer networks · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Interconnection networks and networks-on-chip · 49% Parallel and multicore computing · 36% Processor architecture and microarchitecture · 8%

Topics — the 3 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
multicomputer
0.011991
Network-based multicomputers: an emerging parallel architecture · SC 1991
Processor architecture and microarchitecture
multicore design
0.011991
Network-based multicomputers: an emerging parallel architecture · SC 1991
Parallel and multicore computing
parallel architecture
0.011991
Network-based multicomputers: an emerging parallel architecture · SC 1991

Methods — techniques the papers use, named apart from their topics

host-network interface optimization · 0.0crossbar switching · 0.0star-shaped network topology · 0.0
YearPublicationVenuePosition
1991 Host interface design for ATM LANs
abstract
ATM (asynchronous transfer mode) is an international telecommunications standard designed for broadband integrated services; it is also well-suited for use within local-area networks. ATM LANs can provide the networking support needed for multimedia communication at rates of 100 Mbits/sec and higher. The authors first analyze the protocol processing required to handle ATM communication. Based on this analysis, they then discuss the architectural issues in the design of host interfaces for ATM local-area networks. In particular, they conclude that a simple host interface, which leaves most of the ATM protocol processing to be done by the host computer, supports good performance for data communication (around 100 Mbits/sec). However, to support real-time video and audio communication, the ATM interface should include an embedded processor.>
Eric C. Cooper, Onat Menzilcioglu, Robert D. Sansom, Francois J. Bitz
LCN4
1991 Network-based multicomputers: an emerging parallel architecture
abstract
Multicomputersbuiltaround a general network are now a viable alternative to multicomputersbased on a system-speci~c interconnect because of architectural improvements in two areas.First, the host-network interface overhead can be minimized by reducing copy operations and host interrupts.Second, the network can provide high bandwidth and low latency by using high-speed crossbar switches and efficient protocol implementations.While still enjoying thejexibility of general networks, the resulting network-based multicomputers achieve high performance for typical multicomputer applications that use system-specijic interconnects.We have developed a network-based mtdticomputer called Nectar that supports these claims.
H. T. Kung 0001, Robert D. Sansom, Steven Schlick, Peter Steenkiste, Matthieu Arnould, Francois J. Bitz, Fred Christianson, Eric C. Cooper, Onat Menzilcioglu, Denise Ombres, Brian Zill
SC6
1989 The Design of Nectar: A Network Backplane for Heterogeneous Multicomputers
abstract
Nectar is a “network backplane” for use in heterogeneous multicomputers. The initial system consists of a star-shaped fiber-optic network with an aggregate bandwidth of 1.6 gigabits/second and a switching latency of 700 nanoseconds. The system can be scaled up by connecting hundreds of these networks together.
Emmanuel A. Arnould, Francois J. Bitz, Eric C. Cooper, H. T. Kung 0001, Robert D. Sansom, Peter Steenkiste
ASPLOS2