This paper proposes a statistical approach to modeling the single-sided read static noise margin (RSNM) of a 6-transistor SRAM cell. The proposed modeling considers threshold voltage (Vth), channel length, and width variations. In addition, it considers Vth roll-off and drain-induced barrier-lowering effect of short channel transistors. The proposed method needs only a few samples to calculate the coefficients of the proposed equation. Using the calculated analytic equation, the proposed method can offer feedbacks for design improvements. In goodness-of-fit tests, the proposed method achieved about 89% and 99% improvements in the K-S statistic and the chi-square statistic compared with the Quasi-Monte Carlo method for the same number of samples. Also, compared with the previous method based on an analytic model, the proposed method achieved about 91% and 98% improvements in the goodness-of-fit tests.

This paper presents a logic resynthesizing of FPGA from a downloaded bitstream data for Xilinx 7 series FPGA. This study focuses on the LUT logic reconstructing, which is a primitive logic unit in FPGA. The approach generates all possible logic for a LUT trying to various examples. The generated files are compared with each other that are used to construct the truth table of the LUT. The proposed algorithm extracts the logic configuration by analyzing the bitstream and comparing it with the constructed truth table. The resynthesized circuits provide the input and output pin information assigned in the LUT. The algorithm can be expanded to the previous version of Xilinx 7 series. This study will be helpful for security enhancing of FPGA and development of logic synthesis technique.

Existing computational models of the retina often compromise between the biophysical accuracy and a hardware-adaptable methodology of implementation. When compared to the current modes of vision restoration, algorithmic models often contain a greater correlation between stimuli and the affected neural network, but lack physical hardware practicality. Thus, if the present processing methods are adapted to complement very-large-scale circuit design techniques, it is anticipated that it will engender a more feasible approach to the physical construction of the artificial retina. The computational model presented in this research serves to provide a fast and accurate predictive model of the retina, a deeper understanding of neural responses to visual stimulation, and an architecture that can realistically be transformed into a hardware device. Traditionally, implicit (or semi-implicit) ordinary differential equations (OES) have been used for optimal speed and accuracy. We present a novel approach that requires the effective integration of different dynamical time scales within a unified framework of neural responses, where the rod, cone, amacrine, bipolar, and ganglion cells correspond to the implemented pathways. Furthermore, we show that adopting numerical integration can both accelerate retinal pathway simulations by more than 50% when compared with traditional ODE solvers in some cases, and prove to be a more realizable solution for the hardware implementation of predictive retinal models.

The development of a bioinspired image sensor, which can match the functionality of the vertebrate retina, has provided new opportunities for vision systems and processing through the realization of new architectures. Research in both retinal cellular systems and nanodriven memristive technology has made a challenging arena more accessible to emulate features of the retina that are closer to biological systems. This paper synthesizes the signal flow path of photocurrent throughout a retina in a scalable 180-nm CMOS technology, which initiates at a 128 × 128 active pixel image sensor, and converges to a 16 × 16 array, where each node emits a spike train synonymous to the function of the retinal ganglionic output cell. This signal can be sent to the visual cortex for image interpretation as part of an artificial vision system. Layers of memristive networks are used to emulate the functions of horizontal and amacrine cells in the retina, which average and converge signals. The resulting image matches biologically verified results within an error margin of 6% and exhibits the following features of the retina: lateral inhibition, asynchronous adaptation, and a low-dynamic-range integration active pixel sensor to perceive a high-dynamic-range scene.

This paper presents a CMOS image sensor (CIS) VLSI architecture based on a single-inverter time-to-threshold pulsewidth modulation circuitry capable of operating as low as 330-mV supply voltage while retaining a signal-to-noise ratio of 24 dB; an important characteristic being demanded by very low voltage portable CIS-based equipment such as disposable medical cameras and on-chip autonomous wireless security vision systems. A 64 × 64 pixel array was fabricated using standard 130-nm CMOS process consuming only 5.9 nW/pixel with integration time of 2 ms at +0.5 V supply. The high fill factor of 58% facilitated a better SNR at a low supply voltage when compared with other CIS architectures. The pixel has a dynamic range of 54 dB with 7.8 frame per second.

This live demonstration presents a high fill factor 6 transistor per pixel CMOS image sensor (CIS) based on a single inverter that modulates light illumination to pulse width supporting ultra low supply voltage requirements. It has a compact readout circuitry for pulse-based signal processing without A/D converter at the output. A 64 × 64 pixel array was fabricated using 130 nm CMOS technology. The chip operated under a +VDDas low as 500 mV with power consumption of only 27 nW per pixel. The fill factor is 58%, which is significantly larger than those conventional CMOS imagers.

The nonvolatile memory property of a memristor enables the realization of new methods for a variety of computational engines ranging from innovative memristive-based neuromorphic circuitry through to advanced memory applications. The nanometer-scale feature of the device creates a new opportunity for realization of innovative circuits that in some cases are not possible or have inefficient realization in the present and established design domain. The nature of the boundary, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces challenges in modeling, characterization, and simulation of future circuits and systems. Here, a deeper insight is gained in understanding the device operation, leading to the development of practical models that can be implemented in current computer-aided design (CAD) tools.

Large-capacity content addressable memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moore's Law for a few more years. This paper provides a new approach towards the design and modeling of Memory resistor (Memristor)-based CAM (MCAM) using a combination of memristor MOS devices to form the core of a memory/compare logic cell that forms the building block of the CAM architecture. The non-volatile characteristic and the nanoscale geometry together with compatibility of the memristor with CMOS processing technology increases the packing density, provides for new approaches towards power management through disabling CAM blocks without loss of stored data, reduces power dissipation, and has scope for speed improvement as the technology matures.

The traffic model for the channel assignment scheme based on cell partitioning (CASCP) is proposed. CASCP is the scheme in which different CDMA channels control different sub-areas of a cell area. The sub-area for each CDMA channel is varied according to traffic conditions, those are user velocity, the probability of user moving and interference from sub-area of other cells. CASCP increases the probability of soft handover between cells. We use a simple and accurate approximating method for deriving the channel holding time distribution by a numerical integration approach. We analyze the effects of user mobility on the system performance and compare the performance in terms of handover attempts rate, mean channel holding time, and traffic density.