The protocol VLSI engine (PROVE) is programmable VLSI chipset which can be used to implement several standard communication protocols. The protocol to be implemented is described in a formal specification language called the augmented protocol specification language (APSL). From these formal descriptions, a compiler generates microcode for PROVE. PROVE can process 50000 packets/s for standard protocols such as LAPD and LLC Class 2. It consists of a message parser (MP), message assembler (MA), central controller unit (CCU), and interface with the upper layer. It supports efficient multiplexing operation with zero-overhead context-switching and support for timer maintenance. The paper describes the architectural features of the CCU, the MP, and the MA. A typical protocol implementation using the PROVE chipset is also described. The authors also compare it with other proposals for protocol engines. The first generation of the PROVE chipset has been built and tested.>

MARS (Microprogrammable Accelerator for Rapid Simulations) is a multiprocessor based hardware accelerator capable of efficiently implementing a wide range of computationally complex algorithms. Its architecture is ideally suited for performing event driven simulations of VLSI circuits. The highly pipelined and parallel architecture of MARS provides a performance comparable to existing hardware simulation engines while its highly flexible architecture supports a wide range of applications. Flexibility is achieved through custom designed microprogrammable and reconfigurable VLSI processors. Logic simulation performance of about one million events per second is easily achievable.