Excessive dynamic IR-drop degrades the circuit performance and may lead to functional failure. Existing IR-drop fixing techniques at the placement stage do not consider the time-variant property and thus cannot handle dynamic IR-drop hotspots well. In current practice, designers perform Engineer Change Order (ECO) to move out these hotspot cells based on their experience. In this paper, we present a novel dynamic IR-drop ECO optimization and prediction framework by wise cell movement. We first spread high demand current cells in a global view to stagger their current waveforms. Then, we further move IR hotspot cells close to power/ground (PG) vias for minimizing the resistance from PG pads to their PG pins. Moreover, we propose an accurate machine learning-based dynamic IR-drop prediction model to guide the final cell movement. The features of our model capture power ground network characteristics, timing information, and cumulative current drawn by cells, thus leading to a general model applicable to ECO. Experimental results show that our proposed model precisely predicts dynamic IR-drop after cell movement, and our optimization scheme can substantially alleviate dynamic IR-drop without timing degradation.

In this paper, we have proposed a machine-learning framework to predict the DRC-violation map of a given design resulting from its detailed routing based on the congestion report resulting from its global routing. The proposed framework utilizes convolutional neural network as its core technique to train this prediction model. The training dataset is collected from 15 industrial designs using a leading commercial APR tool, and the total number of collected training samples exceed 26M. A specialized under-sampling technique is proposed to select important training samples for learning, compensate for the inaccuracy misled by a highly imbalanced training dataset, and speed up the entire training process. The experimental result demonstrates that our trained model can result in not only a significantly higher accuracy than previous related works but also a DRC violation map visually matching the actual ones closely. The average runtime of using our learned model to generate a DRC-violation map is only 3% of that of global routing, and hence our proposed framework can be viewed as a simple add-on tool to a current commercial global router that can efficiently and effectively generate a more realistic DRC-violation map without really applying detailed routing.

Clock gating is recognized as one of the most effective techniques to reduce the dynamic power consumption. Many research efforts have been paid to build activity-driven clock trees for low power designs. On the other hand, as the feature size continues to shrink, the on-chip-variation (OCV) effect has become a serious concern, especially for the clock skew of the top-level clock tree. Based on this observation, in this paper, we present the first work for the synthesis of OCV-aware top-level activity-driven clock trees. In our approach, the clock skew variation is considered during the top-level activity-driven clock tree synthesis. Our objective is to minimize the weighted sum of the worst timing slack and the power consumption. Compared with previous works, benchmark data consistently show that our approach can greatly increase the worst timing slack with a small overhead on the power consumption.

We propose a performance-driven cell placement method based on a modified force-directed approach. A pseudolink is added to connect the source and sink flip-flops of every critical path to enforce their closeness. Given user-specified input-output pad locations at the chip boundaries and starting with all core cells in the chip center, we iteratively move one cell at a time to its force-equilibrium location assuming all other cells are fixed. The process stops when no cell can be move farther than a threshold distance. Next, cell rows are formed one at a time starting from the top and bottom. After forming these two cell rows (top/bottom), all remaining movable core cells' force-equilibrium locations are updated. The row-formation-and-update process continues until all rows are formed and, hence, a legal placement is obtained. We have integrated the proposed approach into an industrial automatic placement-and-route flow. Experimental results on benchmark circuits up to 191-K cell (500-K gate) show that the critical path delay can be improved by as much as 17%. Our layout quality is independent of initial placement. We also study the effect on both layout quality and central processing unit time consumption due to the amount of pseudolinks added. We found that the introduction of pseudolink indeed significantly improves the layout quality. We also empirically demonstrated that the proposed approach is effective in reducing the total half-perimeter wirelength metric.

We propose a 3-step approach for whole-chip detail routing. In the first step, we construct a performance-driven Steiner tree for each net ignoring the existence of other nets. In the second step, we optimally assign significant wire segments of all trees to the tracks of a two-dimensional, two-layer grid under the design rule constraint. Finally, in the third step, we complete the remaining local short connection between net terminals and those assigned wire segments and resolve any violations or congestion. We have incorporated this approach into an industrial VDSM design flow. Experimental results on large benchmark circuits implemented in a TSMC 0.18um CMOS process have demonstrated the effectiveness of the proposed approach. We achieve more than 14% improvement over a state-of-art commercial performance-driven router in a critical path delay. Our tool can be viewed as a preprocessor for a router. Users do not have to change their existing design flow. Only a small time-efficient step is needed to achieve the performance gain.

We propose a performance-driven cell placement method based on a modified force-directed approach. A pseudo net is added to link the source and sink flip-flops of every critical path to enforce their closeness. Given user-specified I/O pad locations at the chip boundaries and starting with all core cells in the chip center, we iteratively move a cell to its force-balanced location assuming all other cells are fixed. The process stops when no cell can be moved farther than a threshold distance. Next, cell rows are adjusted one at a time starting from the top and bottom. After forming these two rows (top/bottom), all movable core cells force-balanced locations are updated. The row-formation-and-update process continues until all rows are adjusted and, hence, a legal placement is obtained.

We propose a new layer assignment approach for the klayer Constrained Via Minimization (CVM) problem.We transform the problem into a constrained k-way graph partitioning one.Practicfl issues such as pin-out constraint, over-the-cd constraint, and overlapping between wire segments of the same net, have d been taken into consideration.We propose a motied simdated-anneahng program for the problem.A set of large routing restits generated by a commercial three-layer router has been used to test the effectiveness of the program.Up to 70% reduction of vias has been observed.Assuming an additional fourth layer is avdable, more reduction is achieved.This work is the first to demonstrate the feasibfity of via minimization for practical-sized mtiti-layer layout.It is &o app~cable to future design with more layers.

Retiming relocates registers in a circuit to shorten the clock cycle time. In deep sub-micron era, conventional pre-layout retiming cannot work properly because of dominant interconnection delay that is not available before layout. Although some retiming algorithms incorporating interconnection delay have been proposed, layout information is still not utilized effectively nor efficiently. Retiming and layout is combined for the first time in this paper. We present heuristics for two key problems: interconnection delay estimation and post-retiming incremental placement. An efficient retiming algorithm incorporating interconnection delay is also proposed. Experimental results show that on the average we can improve the circuit speed by 5:4% targeted toward a 0:5um CMOS technology. Scaling down the technology to 0:1um, as much as 25:6% improvement have been achieved. 1 Introduction Retiming is a sequential logic optimization technique proposed by Leiserson and Saxe [1]. It relocates reg...