Demo Data from EDBT 2026 / reviewers in the wild / expert
Hsiang-Ling Li
dblp:21/4832
· DBLP profile ↗
5ranked-venue papers
5as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 2 · 2 first-authorArtificial intelligence and machine learning · 1 · 1 first-authorSystems, architecture and hardware · 1 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Integrated circuit design · 100% | |
| Theoretical computer science
2 papers |
Coding theory · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design › VLSI architecture
survivor memory management |
0.0 | 2 | 1996 | A new architecture for the Viterbi decoder for code rate k/n · IEEE Trans. Commun. 1996 A New Architecture for the Viterbi Decoder for Code Rate k/n1 · IEEE Trans. Commun. 1995 |
Integrated circuit design › digital circuit design › VLSI architecture
viterbi decoder |
0.0 | 2 | 1996 | A new architecture for the Viterbi decoder for code rate k/n · IEEE Trans. Commun. 1996 A New Architecture for the Viterbi Decoder for Code Rate k/n1 · IEEE Trans. Commun. 1995 |
Integrated circuit design › digital circuit design
VLSI architecture |
0.0 | 2 | 1996 | A new architecture for the Viterbi decoder for code rate k/n · IEEE Trans. Commun. 1996 A New Architecture for the Viterbi Decoder for Code Rate k/n1 · IEEE Trans. Commun. 1995 |
Coding theory › error-correcting codes
convolutional codes |
0.0 | 2 | 1996 | A new architecture for the Viterbi decoder for code rate k/n · IEEE Trans. Commun. 1996 A New Architecture for the Viterbi Decoder for Code Rate k/n1 · IEEE Trans. Commun. 1995 |
Coding theory › error-correcting codes › convolutional codes › convolutional code decoding
viterbi decoding |
0.0 | 2 | 1996 | A new architecture for the Viterbi decoder for code rate k/n · IEEE Trans. Commun. 1996 A New Architecture for the Viterbi Decoder for Code Rate k/n1 · IEEE Trans. Commun. 1995 |
Methods — techniques the papers use, named apart from their topics
hierarchical design · 0.1foldable topology · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Motion estimation of two-dimensional objects based on the straight line hough transform: A new approach
Hsiang-Ling Li, Chaitali Chakrabarti |
Pattern Recognit. | 1 |
| 1996 | A new architecture for the Viterbi decoder for code rate k/nabstractA novel VLSI architecture is proposed for implementing a long constraint length Viterbi decoder (VD) for code rate k/n. This architecture is based on the encoding structure where k input bits are shifted into k shift registers in each cycle. The architecture is designed in a hierarchical manner by breaking the system into several levels and designing each level independently. The tasks in the design of each level range from determining the number of computation units, and the interconnection between the units, to the allocation and scheduling of operations. Additional design issues such as in-place storage of accumulated path metrics and trace back implementation of the survivor memory have also been addressed. The resulting architecture is regular, has a foldable global topology and is very flexible. It also achieves a better than linear trade-off between hardware complexity and computation time. Hsiang-Ling Li, Chaitali Chakrabarti |
IEEE Trans. Commun. | 1 |
| 1995 | A new Viterbi decoder design for code rate k/nabstractA novel VLSI architecture is proposed for implementing a long constraint length Viterbi decoder (VD) for code rate k/n. This architecture is based on the encoding structure where k input bits are shifted into k shift registers in each cycle. The architecture is designed in a hierarchical manner by breaking the system into several levels and designing each level independently. At each level, the number of computation units, the interconnection between the units as well as allocation and scheduling issues have been determined. In-place storage of accumulated path metrics and trace back implementation of the survivor memory have also been addressed. The resulting architecture is regular, flexible and achieves and better than linear tradeoff between hardware complexity and computation time. Hsiang-Ling Li, Chaitali Chakrabarti |
ICASSP | 1 |
| 1995 | A New Viterbi Decoder Design for Code Rate K/NabstractA novel VLSI architecture is proposed for implementing a long constraint length Viterbi Decoder (VD) for code rate k/n. This architecture is based on the encoding structure where k input bits are shifted into k shift registers in each cycle. The architecture is designed in a hierarchical manner by breaking the system into several levels and designing each level independently. At each level, the number of computation units, the interconnection between the units as well as allocation and scheduling issues have been determined. In-place storage of accumulated path metrics and trace back implementation of the survivor memory have also been addressed. The resulting architecture is regular, flexible and achieves a better than linear tradeoff between hardware complexity and computation time. Hsiang-Ling Li, Chaitali Chakrabarti |
ISCAS | 1 |
| 1995 | A New Architecture for the Viterbi Decoder for Code Rate k/n1abstractA novel VLSI architecture is proposed for implementing a long constraint length Viterbi decoder (VD) for code rate k/n. This architecture is based on the encoding structure where k input bits are shifted into k shift registers in each cycle. The architecture is designed in a hierarchical manner by breaking the system into several levels and designing each level independently. The tasks in the design of each level range from determining the number of computation units, and the interconnection between the units, to the allocation and scheduling of operations. Additional design issues such as in-place storage of accumulated path metrics and trace back implementation of the survivor memory have also been addressed. The resulting architecture is regular, has a foldable global topology and is very flexible. It also achieves a better than linear trade-off between hardware complexity and computation time. Hsiang-Ling Li, Chaitali Chakrabarti |
IEEE Trans. Commun. | 1 |