Techniques for the foreground calibration of split capacitor successive approximation register (SAR) are discussed. The used methods of digital calibration requires a digital post-processing that can be a limit for the resulting overhead. The presented techniques allow directly obtaining the digital output. Two methods address the mismatch among the unit elements in the most significant byte (MSB) segment and the mismatch at the MSB-LSB interface. A 16-bit SAR ADC with a sampling rate of 1MS/s employs both calibration techniques and verifies the methods. The simulation results show a Schreier merit of 166.3 dB, a signal-to-noise-and-distortion ratio (SNDR) of 87 dB, and an SFDR of -100 dB. A chip fabricated in a 180-nm Bipolar-CMOS-DMOS (BCD) process almost obtains the expected SNDR. The experimental result shows that the spurious-free dynamic range (SFDR) improves from 70.71 to 93.29 dB.

Many applications of machine learning (ML) have been integrated into edge devices with their low communication latency. In edge computation, the reprocessing of redundant data results in considerable energy waste. The prior research utilized a digital-delta-digital-sigma computing-in-memory (CIM) scheme to mitigate this redundancy. However, the 7-bit LSB-first ADC resulting from the near-zero-mean output distribution led to excessive area and latency overhead. The following digital adder further induced power consumption and latency. We propose a digital-delta-analog-sigma CIM macro incorporating an analog sigma converter (SC) for edge computation, involving a switch-capacitor integrator with a floating inverter amplifier (FIA) and a quantizer. The increased analog swing of the sigma integrator leads to the expanded output distribution, thereby maintaining comparable accuracy with a relaxed quantizer resolution. The simulation demonstrates that our strategy contributes to a 57.5% reduction in latency, a resolution decrease of 2 bits, and better energy efficiency. These improvements can potentially enhance energy efficiency and computational speed in edge computation devices.

This paper presents a hybrid single-inductor bipolar triple-output (SIBTO) DC-DC converter for active-matrix organic light-emitting diode (AMOLED) displays. Generating the bipolar rails$V_{\mathrm {OP}}$and$V_{\mathrm {ON}}$for the pixel array and the analog rail AVDD for the source driver with a single inductor greatly reduces the system size and cost. This work adopts the floating negative output topology for an ultra-clean positive output. In addition, we propose a push-pull charge balancer to compensate and regulate the$V_{\mathrm {OP}}$, improving the line and load regulation with continuous currents and acceptable power consumption. This work also proposed a slow-comparator based ordered power distributive control (SC-OPDC) to regulate the AVDD with a pulse-skipping scheme to reduce the power loss. The designed power transistor buffers with adaptive deadtime control improve power conversion efficiency and decrease the required minimum load current of AVDD. The proposed SIBTO converter, implemented in 0.18-$\mu \text{m}$BCD process, operates at 1.67 MHz. It achieves a peak efficiency of 94.1% at 0.88 W output and a maximum output power of 3.67 W with an efficiency of 87%. The maximum output voltage ripples are 5 mV, 17 mV, and 7.5 mV for$V_{\mathrm {OP}}$,$V_{\mathrm {ON}}$, and AVDD, respectively.

This paper reports a reference-less frequency- detector-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring wide frequency acquisition. We use a current-starved ring oscillator controlled by a 5-bit resistive digital-to-analog converter to maintain quarter-rate operation, supporting a capture range of 110.4%. By the virtue of a deliberate-current-mismatch charge pump pair, we form the single-sided capture scheme in the frequency detection characteristic, eliminating the power-hungry circuits in the high-speed clock and data paths. Employing a hybrid control circuit, the proposed BBCDR automates frequency acquisition and phase tracking in the overall 32 bands. Prototyped in a 65-nm CMOS, the BBCDR covers a wide data rate from 10.8 to 37.4 Gb/s, achieving an acquisition speed of 4.63 [(Gb/s)/$\mu \text{s}$] and an energy efficiency of 1.3 pJ/bit.

This paper describes the design and the performance comparison of four different configurations of power stages of switching DC-DC buck converters with high switching frequency (f = 100 MHz), studied for automotive applications in the post-regulated domain. Different transistors are used for both power stage and pre-driver chain, and the solutions are compared in terms of efficiency and maximum input voltage. A rough estimation of the area consumption of each of the four configuration is also provided. The circuits have been optimized to have maximum efficiency with V in = 3.6 V, V out = 1.8 V and I load = 1 A, which are typical values in automotive post-regulated applications.

Nowadays, the field of microelectronics has become the drive for the advancement of the times, which promotes new demands on the cultivation of the students in colleges and universities. In order to keep up with the trend of the global engineering educational reform, three important reforms in education have been in progress step by step, including classroom teaching, innovative training and virtual laboratories. At first, for enhancing and integrating the existing courses related to the circuit, so that the students can comprehend the existing knowledge much more effectively, an important and effective curriculum reform has been performed by combining “Circuit Analysis” and “Analog Circuit Foundation” into one course; Then, innovative training has been carried out to cultivate the team skills among the students; Finally, in consideration of the rapid development of the electrical and electronic experiment, the conventional laboratory equipment may not satisfy the demand of every student due to financial constraints, therefore, the construction of virtual simulation experiment center is an efficient way to break this bottleneck. As a result, the atmosphere of academic innovation of the pursuit of truth, advocacy of science, brave exploration, dare to practice have been formed in colleges and universities through the above innovative engineering education reform.

Multi-bit architectures of incremental converters are discussed. The use of a hybrid scheme and multi-rate operation reduces the consumed power. Methods for canceling or significantly reducing the error caused by the mismatch between unit capacitors are proposed. Behavioral simulation results prove the effectiveness of the solutions.

Advanced communication systems, smart and biomedical technologies have led to the need of complex laser systems. The traditional solutions, inherited by the traditional optical communication architectures, start to present limitations due to the high output compliance and high power consumption. Moreover, the common anode topologies present scarce adaptability to multi-purpose systems implemented in present systems on chip. This paper presents and discusses DAC architectures for a common cathode current driver suitable for laser system applications. The discussion is supported and complemented by results collected from simulations at the transistor level using a 0.13-μm BiCMOS technology.

This paper presents the design of an ultra high speed Flash ADC, designed in a 28-nm CMOS technology. The circuit exploits the metastability of the voltage comparators in order to enhance the converter resolution. The used technique allows achieving 5-bit of resolution with only 16 voltage comparators, reduces the input capacitance of the converter, lowers the power consumption and improves the area occupied. Clocked at 10 GHz, the obtained SNDR from post-layout simulations is 30.41 dB for an input signal of 900 mVpk-pkat 5 GHz. The simulated DNL and INL are within 0.3 LSB and 0.34 LSB, respectively. Consuming 55 mW, the achieved FoM is 0.21 pJ/conv-step.

A method to calibrate the timing skew of flash-assisted time-interleaved analog-to-digital converters is proposed. The calibration is performed in two steps and is composed of a variance based and of an auto-correlation based timing-skew estimation. Both estimation phases are performed in the digital domain and require low hardware. In addition, channel randomization is facilitated with the use of the proposed method. Behavioral simulations have demonstrated that the method greatly improves the ADC performance and is effective up to the Nyquist frequency.

This paper presents a capacitive array optimization technique capable to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for smart sensor specifications. Monte Carlo simulation results show that the proposed optimization technique makes the SFDR, SNDR and (Signal-to-Noise Ratio) SNR better definitely concentrated, which means with a spread between maximum and minimum value much smaller than the one obtained by conventional calibration techniques. This gives rise to more stable and better performances. The averaged SFDR improves from 72.9 dB to 91.1 dB with σu = 0.4%, the 18.2 dB improvement required an off-line processing and a small digital logic circuits.

This paper presents a dual-loop digital low-dropout regulator (DLDO) with asynchronous-flash (AF) binary coarse tuning for fast transient response. In steady state, the DLDO operates with a unary-weighted low power fine-tune loop to improve the regulation accuracy. Besides, a freeze mode is also employed to further reduce the power budget and to eliminate the limit cycle oscillation phenomenon. When a load-transient is detected, the proposed AF bidirectional shift register will direct the binary-weighted power switches for coarse and fast tuning. The prototype is fabricated in a 28nm bulk CMOS process. With VIN=0.5V and 50mV dropout, the AF-DLDO can deliver 33mA output current and consume only 10.5μA quiescent current. We measured 102mV voltage undershoot for a 30mA/20ns load step, showing a 0.11ps FOM.

This paper presents an approximated linear model for memristive devices. Because of the abundance of technology solutions, the many models so far presented, more or less complicated, are generally technology-specific and this represents a problem for resistive memory designers who need to test the analog and digital periphery without affecting the computational costs. For this reason, an approximated model, formally derived from the traditional one, has been conceived and tested with a Verilog-A implementation. Based on the linear model, our approximation preserves a good fit with the experimental data, ensuring scalability and generality. Moreover, very important for memory applications, the computational costs and resources are considerably reduced. The model validity has been proven in some design cases, while model parameters have been extracted from measurements carried out on devices implemented in a 250-nm BiCMOS technology.

This paper presents two design considerations for integrated high-voltage DC-DC converters in automobile and industrial applications. The proposed solutions include (i) a quasi soft-start technique using over-current protection (OCP) circuits and limited duty cycle control and (ii) a technique to drive a floating load-side switch that suppresses the effect of bond-wire bouncing on its gate-source voltage. The first technique avoids the conventional, overhead start-up circuits and significantly reduces the converter startup time. The second technique gains importance primarily from device reliability viewpoint in high-voltage (HV) conditions. The effectiveness of the proposed techniques has been verified with simulations at the transistor level using a 110-nm BCD technology.

This paper describes a novel sub-threshold voltage reference generator suitable for very low power and very low voltage wearable systems. Indeed, the circuit, designed and extensively simulated in a standard 0.18-μm CMOS technology, generates a 51.3-mV output voltage with a nominal supply voltage of 0.5 V and consumes as low as 185 nW. Design optimisation and a first order temperature compensation allow achieving a temperature coefficient of 25.4 ppm/ C in the temperature range from -40 to 125° C. The proposed architecture optimizes the output noise performance by minimizing the current mirrors flicker and thermal noise contributions which, in conventional schemes, severely affect the output node. In addition, the same circuital arrangement allows obtaining high power supply rejection (PSR). The simulated root mean square output noise is 1.6 μV in the frequency range from 0.1 Hz to 10 Hz, while the PSR is -76 dB at 100 Hz, a remarkable value.

This paper presents linearity enhancement capacitor re-configuring technique to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of ADC simultaneously without sacrificing the sampling rate in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioural Monte-Carlo simulations are presented to demonstrate the effect of the proposed method where no complex least-mean-square (LMS) algorithm. Simulation results show that with a mismatch error typical of modern technology, the SFDR is enhanced by about 18 dB and the SNDR is 15 dB better with the proposed technique for a 14-bit SAR ADC, which makes it suitable for accurate and linear smart sensor nodes in wearable sensing systems.

This paper presents a level-shifting technique for high-voltage power converter applications. The proposed circuit effectively combines capacitive and active coupling of the input low (high) side signal to the output high (low) side to reduce the propagation delay of the level-shifting operation. By using the resulting circuit, (i) the high-side PMOS switch is driven at high speed and (ii) a quasi-zero voltage switching (ZVS) of the low side NMOS switch is achieved. The circuit has been designed and simulated at the transistor level using a 0.18-μm BCD process. At the high-side, remarkable simulated average level-shifter propagation delay and total driving delay have been achieved: 0.5 ns and 1.9 ns, respectively. The proposed level-shifter consumes 48.5 μA of average current.

This paper discusses the use of a low gain amplifier and a passive switched-capacitor (SC) network to enable the SC integrator function. The method is applied to a delta-sigma modulator to achieve high resolution as proved by the 65-nm CMOS technology test vehicle. Compared with the conventional operational amplifier (op-amp)-based SC integrator, this solution utilizes a low-gain open-loop amplifier to drive a passive SC integrator with positive feedback. Since the open-loop amplifier requires a low dc gain and implements an embedded current adder, the power consumption is very low. Power reduction for single bit is obtained by using passive feedforward with built-in adder to assist the first amplifier. The low swing obtained at the output of the active blocks relaxes the slew rate requirement and enhances the linearity. Implemented in 65-nm digital CMOS technology with an active area of 0.1 mm2, the test chip achieves a dynamic range of 91 dB, peak signal-to-noise ratio of 88.4 dB, peak signal-to-noise-plus-distortion ratio of 88.2 dB, and a spurious free dynamic range of 106 dB while consuming 73.6 μW in a 25-kHz signal bandwidth at 1 V supply, yielding a FoMWaldenof 70 fJ/conv-step and FoMSchreierof 176 dB.

In this paper a rad-hard design flow for emerging non-volatile memories is discussed. The always growing demand of memory performances is driving to an increasing investigation in new technologies; many emerging technological solutions have been introduced and, as all of them are still an embryonic stage, it is necessary to improve and optimize their characterization process in order to achieve as soon as possible the reliability necessary to stand out in the market. Among them, the resistive memories have recently raised a significant interest for space and high-energy applications. In this scenario, hence, it may be effective and crucial to design an architecture capable to manage different demands like the use in radiation environment. At this purpose, a radiation-hardened design of a 1Mbit resistive non-volatile RAM providing full bit DMA access is proposed. A basic RRAM cell and its structure are explained and the radiation hardened architecture that includes a redundant differential approach presented.

This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.

This paper presents techniques for increasing communication data rates for OOK modulated signals in the case the carrier frequency is generated by a cross-coupled pair LC oscillator. The proposed circuitry completely turns off the transmitter during the transmission of “0” bit and oscillation occurs only when the data bit is “1” to reduce power consumption. The data bit controls the steady state bias current and the operation of the oscillator. The communication data rate is limited by the turn-on and turn-off time of the LC oscillator. In order to speed up the turn-on time of the oscillator, in addition to bias current, an extra current source is used during the build-up of the oscillator. The decay time of the oscillator when the data is switched from “1” to “0” is accelerated by shortening the inductor connections. The concept is demonstrated through the design of an LC VCO in 0.18 μm CMOS technology. The LC oscillator is designed to oscillate in MedRadio band at 416 MHz frequency. Simulation results show that the proposed architecture shortens the turn-on time from 86.5 ns to 24 ns and the turn-off time from 101 ns to 5.93 ns. With the additional techniques, the maximum achievable communication data rate is increased by more than 6 times.

This paper presents the design of an hybrid course-fine time to digital converter for low power applications. The core of the circuit consists of two current-mode SAR analog to digital converters working in a time-interleaved fashion. The TDC has been fully simulated at the transistor level with a 0.13-μm CMOS technology. The paper discusses the design details and the digital calibration techniques required to achieve a single-shot resolution of about 27 ps while keeping the power consumption below 600 μW.

This paper describes a single op-amp 0+2 ΣΔ architecture and design considerations to achieve 12-b resolution on a 2-MHz bandwidth. The proposed topology combines op-amp reduction and MASH techniques. In particular, the second-order ΣΔ stage uses direct synthesis of the noise transfer function (NTF) and employs only one op-amp. The use of multi-bit quantization on both stages increases the resolution of the modulator and reduces the output swing of the op-amp. The mismatch of the multi-level DACs can be compensated for with DEM while the mismatch between the two stages can be canceled in the digital domain. Simulation results, carried out at the transistor level with a 0.18-μm CMOS technology, verify the effectiveness of the proposed architecture. The simulated FoM is 104 fJ/conv-step.

A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.

This paper proposes the use of sampled-data operation in op-amps. The technique favors very low supply voltage and micro-power. After discussing the method at a general level, a possible sampled-data scheme is analyzed. Simulations with a low threshold technology show that a 0.5-V supply is possible. A version of the circuit, which has been integrated by using a standard 0.18-μm CMOS technology (with high thresholds), is able to operate at 0.65-V supply voltage. Simulation results show 42.5 dB of DC gain and 2.5-kHz bandwidth with 0.5-pF load capacitor. The power consumption is 63 nW. A pseudo-differential scheme doubles the consumed power and increases the DC gain by 6 dB.

A novel current mode Capacitor Based Sine-Shaped (CBSS) Digital-to-Analog Converter (DAC) for Continuous-Time (CT) Sigma-Delta (ΣΔ) modulators, enabling smooth zero current transitions and greatly reducing the clock jitter noise, is described. The circuit is switched capacitor based and uses a cosine-wave voltage reference instead of constant current. The output is a sine-shaped waveform with precise zero transitions. Locking the reference cosine-wave voltage and the clock employed for data sampling ensures a virtual immunity to clock jitter. The use of a cosine-wave as reference and a constant capacitance loading the reference generator facilitates impedance matching thus making the scheme suitable for very high sampling rate. Moreover, the good matching between capacitors determines the accuracy of the integrators' time constant and multi-bit linearity of the proposed DAC. The feature of the method has been verified with behavioral simulations and tested in a second order ΣΔ modulator.

A magnetic Hall sensor working in the current-mode is presented. The proposed sensing device is composed by two Hall plates able to provide a differential current at the output nodes. The sensor, fabricated in a standard 0.18-μm CMOS technology, uses the spinning-current technique to compensate for the offset and obtains a sensitivity IHall/(B⊥Ibias) better than 0.02 T-1for magnetic fields ranging from 0 to 10 mT.

This paper describes a multi-bit third-order incremental analog-to-digital (ADC) architecture and design considerations to achieve 18-bit resolution. The architecture uses multi-bit quantization in order to increase resolution and reduce the output swing of op-amps. The non-linearity due to the mismatch of unity elements of multi-bit DAC is properly compensated for with Smart-DEM algorithm. This 2+1 incremental architecture achieves 18-bit resolution with a 3-bit quantizer. Simulation results verify the target resolution achieved with 61 clock periods despite a large unity element mismatch (3σ = 0.5%).

This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulations, as well as measured results. Performances of both switching methods are demonstrated in 90 nm CMOS. Measurement results of power, speed, and linearity clearly show the benefits of using Vcm-based switching.

This paper presents the design of a third-order ΣΔ modulator targeted for WCDMA applications. The architecture uses two operational amplifiers and distributed fully digital feed-forward paths to minimize the output swing of op-amps. Simulation results show that first and second integrator output swings are reduced by 88% and 75%, respectively. Post-layout simulation results of the modulator, designed in 65-nm CMOS technology, give a SNDR of 83 dB over a signal bandwidth of 2.2 MHz. The power consumption is 2.3 mW and the achieved FoM is equal to 172.8 dB.

This paper describes the design method for highorder multi-bit incremental converters aiming at high resolution (> 14 bits) with Smart-DEM algorithm. Traditional 2ndand 3rd-order incremental ADCs use 1-bit quantizer. These structures lead to long conversion time for each sample to achieve the expected resolution and high power consumption due to the large output swing of the op-amps. Also, the fractional coefficients along the accumulation path that avoid instability degrade the performance. On the contrary, modulators employing multi-bit quantizer and DAC do not suffer from these problems. Although the mismatch of unity elements in the DAC causes non-linearity issue, this can be suppressed by Smart-DEM algorithm. Because the Smart-DEM algorithm is quite compact and easy to implement, the modulator benefits extra bits performance directly from the multi-bit DAC with affordable digital circuits overhead. In this paper several structures for incremental ADCs utilizing multi-bit quantizer are presented. The positive-and-negative DAC and the Smart-DEM algorithm are explained. With 3-bit quantizer, the simulation results show that the 2nd-order incremental ADC obtains 18-bit resolution with 256 clock periods.

This paper presents design and experimental results of a second-order, discrete-time, quadrature band-pass ΣΔ modulator targeted for wireless body area networks. The non-conventional architecture locks the intermediate frequency (IF) to the sampling frequency. Measurement results collected from a CMOS 0.18-μm prototype achieves a peak SNR of 55 dB over 100-kHz bandwidth and 40-dB SNR over 2.6-MHz bandwidth for a sampling frequency of 20 MHz with 1.96 mW power dissipation.

A second-order multi-bit hybrid continuous-time (CT) ΣΔ modulator has been implemented in a 65-nm CMOS technology. The circuit ensures jitter immunity granted by the use of multi-rate switched-capacitor (SC) DACs. An auxiliary digital assistance technique reduces integrators output swing. The modulator provides 10.8 bits of resolution over a signal bandwidth of 1.1 MHz and a spurious free dynamic range (SFDR) of 78 dB. The chip draws 1.1 mW from a 1-V supply.

Performance of wireless sensor systems are evaluated on the basis of the quality of data communication and efficiency of power transmission. This work presents the design methodology of a miniaturized tag antenna for remote powering of wireless sensor systems at 2.45 GHz ISM band. Accurate simulations of the rectifier input impedance aimed at the maximization of transmitted power are presented. Simulation results combined with simple transmitting antenna scattering parameters and cable loss measurements provide straightforward characterization of the fabricated tag antenna. The experimental measurements on a 12×10mm miniaturized antenna designed with the proposed approach show a gain of -5.9 dB close by 0.8 dB to the simulation results.

An intelligent power feedback design for remotely powered freely moving animal telemetry systems is described. The system uses an optimized wireless power transmission that utilizes multiple transceiver coils. An intelligent mouse cage with controller unit of the feedback system are proposed. System description, experimental setup and measurements of the remotely powered implantable monitoring system are presented.

This paper presents a new concept for an effective design of quadrature band-pass ΣΔ modulators with built-in Signal Transfer Function (STF) filtering action and discusses the architectural level implementation issues for second and third order modulators based on delay line topologies. The methodology uses an architecture which locks the intermediate frequency (IF) to the sampling frequency for both STF and Noise Transfer Function (NTF). Robustness of the structure against the mismatch is analyzed with interference tones placed in different locations of the receiver spectrum, including the image band. Simulations at the behavioral level verify the architecture implementation and the effectiveness of the approach.

Multistage operational amplifiers suitable for nanometer-scale CMOS technologies and low-voltage applications are described. The low intrinsic gain of transistors is compensated for with cascade of single-stage amplifiers. Techniques for compensations are revisited and the optimal solution identified. An example of a novel scheme that achieves 67 dB of DC gain, 320 MHz of bandwidth and 61 degrees of phase margin is presented. The power consumption is as low as 0.24 mW with a slew rate of 84.5 V=µ s. The CMOS technology is 65 nm; the design uses only minimum channel length transistors.

This paper presents a design methodology for dithered bus-splitting Multi stAge noise SHaping (MASH) digital delta-sigma modulators (DDSMs). Rules for selecting the appropriate wordlengths of the constituent DDSMs are derived which ensure that the spectral performance of the bus-splitting architecture is comparable to that of the conventional design but with less hardware. Behavioral simulations are presented which confirm the theoretical predictions.

This paper proposes a new low order time variant digital ΣΔ MASH modulator for fractional frequency synthesizers. The phase noise spectrum is improved as the spur tones from the fractional modulation are disabled. The usage of low order time variant MASH architectures reduces the number of levels that control the programable divider, reducing therefore the complexity and power requirements of the synthesizer.

An architecture for low-power ΔΣ modulators suitable for high-resolution portable sensor systems is presented. The circuit uses a single operational amplifier to achieve a third-order noise shaping. The two-stage op-amp employs a boosting technique that increases by 5 the slew-rate. The circuit, simulated at the transistor level using a conventional 0.18-μm CMOS technology, obtains a peak SNDR of 88 dB over an input signal bandwidth of 100 kHz. The simulated power consumption is 125 μW with a 1.5-V supply voltage. The achieved Figure of Merit (FoM) is 31 fJ/conversion-level.

A novel multi-rate Time-Interleaved Current Steering Digital to Analog Converter with unity element sharing is presented. Proposed 12-bit DAC is simulated in 90nm CMOS technology. The implemented DAC is divided to two segments, MSB and LSB segments, each having 6 bits of resolution. Taking advantage of the oversampling requirement due to the reconstruction filter at the DAC output, the MSB segment is further separated to 6 subDACs to implement time-interleaved and return-to-zero techniques. Time interleaved technique reduces the switching speed of each individual unit element to 1/6thof the sampling clock frequency and RTZ technique improves the linearity of the DAC. Simulations show that employed technique improves the linearity over 6dB with an SFDR of 85dB with 6GS/s sampling frequency and 460MHz input frequency. The DAC draws 13mA from a 1.5V supply. The expected active area of the DAC is 1mm2.

This paper presents a new solution to obtain a spurs-free high precision amplifier. The method involves input chopping and correlated double sampling signal de-chopping. The offset is removed by using DC coupling. The proposed method, verified with transistor level simulations, is applied to a rail-to-rail input amplifier with 187 dB DC gain and 13.7 μA current consumption.

This paper presents an All Digital PLL (ADPLL) based on a first order noise shaping Time-to-Digital Converter (TDC). The architectures of two state-of-art ADPLLs and a state-of-art Gated Ring Oscillator (GRO) TDC are described. The architecture of the GRO TDC is compared with that of the proposed Local Oscillator based TDC (LO TDC) in terms of spectral performance. Behavioral Verilog-AMS models of the LO, exact LO, and exact GRO TDCs are described briefly. Finally, the Verilog-AMS models of three ADPLLs, including the TDC models, are compared by means of simulations.

In this paper we present a MASH bandpass ΣΔ modulator for WCDMA applications. The signal bandwidth of the proposed modulator is 10 MHz, centered around an intermediate frequency (IF) of 70 MHz. Each ΣΔ modulator of the MASH structure is based on a two-path architecture, which allow us to obtain the desired in-band noise shaping zeros and reduce the power consumption. The ΣΔ modulator is implemented using a 0.18-nm CMOS technology and a sampling frequency of 180 MHz. The simulations at transistor level show a resolution of about 13 bits, with a bandwidth of 10 MHz, and a power consumption of about 90 mW, with a supply voltage of 1.8 V, resulting in a figure of merit (FoMBP) as low as about 0.15 pJ/conversion-level.

A fully digital feedforward ΣΔ modulator is described. The technique, here applied to a second order low-pass modulator, strongly reduces the operational amplifiers output swing, thus allowing the use of power effective single stage architectures. The method enables reduced slew-rate requirements and allows operation at lower power supply voltages. The proposed technique has better or comparable performance than more power hungry conventional analog and digital feedforward solutions. Behavioral simulations and a sensitivity analysis demonstrate the effectiveness of the approach.

A double sampled second order ΣΔ modulator with an analog look ahead (ALA) approach is presented. The proposed architecture provides an extra clock period to be used for the quantization. The feedforward path in both integrators allows the further reduction of the output voltage swing, relaxing also the slew-rate requirements of the op-amps. Moreover, the modulator enables the reduction of the number of quantization levels in the quantizer, thus the overall power consumption of the modulator would be significantly reduced. The proposed solution has been simulated at behavioral level by considering an improved model which takes into account the slew-rate and bandwidth limits.

By splitting the input sampling capacitor of a SigmaDelta modulator into several time-interleaved branches, FIR filtering can be incorporated into the signal transfer function. Doing so imposes little or no overhead in the design of the opamps. Simulations of a 3rd-order modulator demonstrate that up to 65 dB of anti-aliasing can be obtained with 5 time-interleaved switched capacitor branches.

The design of a quadrature bandpass Sigma-Delta (ΣΔ) ADC build by cascading two complex modulator is presented. The utilization of cascading enables the independent control of zeros of the noise transfer function. Design method and simulation results including errors due to non-idealities as well as limits of a fourth order scheme are presented. The flexibility of placing notches at critical frequency and benefits are outlined.

A two stage op-amp with an effective technique to enhance slew-rate and gain is presented. The enhancement is provided by an auxiliary monitor circuit which is activated in slewing conditions, but can contribute to the gain in normal conditions. The amplifier, simulated in a 0.18 Omegam technology, achieves 74 dB DC gain, 160 MHz bandwidth and 26.8 V/mus slew-rate for a load capacitance of 1.75 pF with 362 muW power consumption, considering a supply voltage of 1.8 V.

Design strategies for power effective medium/high resolution Successive-Approximation ADC are discussed. The study considers reducing the power of the capacitive array with suitable capacitive attenuators that do not need using non-unity capacitors. The design of minimum power comparators is analyzed and a novel comparator scheme, named time-domain comparator, is described. The proposed methodologies, verified with a test design, is capable to provide 12-bit with 50-kHz signal band and 1-V supply. The achieved FoM is 14 fj/conv-level, which is well below the state-of-the-art.

Design techniques for single inductor multiple output (SIMO) DC-DC buck converters are presented. The suitable control of a multiple feedback loop enables the sharing of a single inductor with many outputs with a good stability and limited cross regulation. The method has been verified with simulations at the behavioural and transistor level to obtain four independent regulated output voltages ranging from 0 V to 1 V below the power supply voltage. The use of a suitable analog processing of errors allows obtaining a power efficiency as high as 86%.

The performance of a sigma-delta ADC can be increased by increasing one or more of the main three parameters, over-sampling ratio, the order of the modulators and the number of bits used. Increasing each of these parameters presents a degree of challenge (i.e., the increase in the over-sampling ratio is limited by the technology and the power consumption requirement). This paper presents a new method to obtain 2ndorder noise shaping from two 1storder, time interleaved modulators by applying cross-coupling of quantization noise between the two paths. The proposed sigma- delta ADC is implemented in 90 nm CMOS technology.

The design strategies for band-pass SigmaDelta modulators are discussed. This paper studies two different approaches: the use of resonators and the synthesis of the noise transfer function (NTF) starting from a closer function. The use of a MASH configuration to obtain multiple zeros or splitting the complex zeros of the NTF is also discussed. The sensitivity to components mismatch of the proposed solutions is studied to identify advantages and limits of various presented architectures. Results show that mismatch errors in the fraction of percent range do not degrade the SNR significantly.

Low distortion and reduced swing can be achieved by designing the DeltaSigma modulator with an input feedforward path. Furthermore, the modulator stability can be enhanced and the requirements on the preceding anti-aliasing filter can be relaxed by designing the DeltaSigma modulator for a flat unity-gain signal transfer function (STF). Previously-developed DeltaSigma modulators with analog feedforward (AFF) achieved a unity-gain STF. However, their performance is limited by the need for an analog adder before the quantizer. Previously-developed DeltaSigma modulators with digital feedforward (DFF) eliminated the need for this analog adder. However, their STF was not unity. In this paper, a technique for designing digitally-enhanced DeltaSigma modulators with both a DFF path and a unity-gain STF is presented. A 2nd-order DFF DeltaSigma modulator with a unity-gain STF is then proposed. Its key features include reduced signal swing at the opamp outputs, reduced sensitivity to integrator nonlinearities, and robustness to DeltaSigma modulator coefficient variations. Behavioral simulation results confirm its performance advantages versus previously-developed AFF and DFF DeltaSigma modulators.

Analog-to-digital converters are one of the essential components in modern highly integrated Power Management ICs (PMICs). Although, the conversion time and resolution requirements are relatively easy to achieve, the requirements such as extended input signal range exceeding the system supply level, low power consumption for higher system efficiency, and resilience to heavy substrate and supply noise complicate the design of the ADC. In this paper, an 11 bit Sub-Ranging SAR analog to digital converter designed for power management systems is presented. The supply voltage and the reference voltage of the converter are both equal to 2.75 V while any of its 8 input channels can vary between 0-5.5 V range (or twice the reference voltage). The integral and differential nonlinearities of the converter are 0.38 and 0.45 LSB respectively. The ADC draws only 140μA of quiescent current and has a conversion time of 10μs.

Noise-coupled multi-cell delta-sigma ADCs are presented. By providing quantization noise coupling between identical delta-sigma ADCs, one can effectively raise the order of the modulator. Cross-coupled noise injection also provides an efficient way to realize higher-order time-interleaved ADCs.

In recent years, continuous research efforts have been concentrating in increasing ΣΔ modulators operating frequency, while still reducing their power consumption. Indeed, when the ΣΔ modulator figure of merit (FoM) is less than 1 pJ/conversion, the decimation filter power consumption becomes a critical parameter. This paper presents a low power sin3FIR filter for ΣΔ modulators. The proposed filter implements a decimation by 4, operating at 64 MHz and consumes only 0.1 pJ/sample processed. The circuit has been implemented and simulated in a 0.18-μm CMOS technology, showing an overall power consumption reduction of about 67% with respect to a conventional design. Finally, a silicon area reduction of 17% in the combinatory part of the filter can also be achieved.

An audio band sigma-delta ADC based on a new time-interleaved xx scheme isdescribed. The circuit achieves a very low power operation with the large dynamic range required for audio applications. This modified two channel time-interleaved scheme improves the power efficiency thanks to halved operating frequency in the paths, and a reduced number of levels in ADC and DAC. This sigma-delta modulator fabricated in a 0.18 μm CMOS process uses 1.8 V supply and ±0.5 V input range. Experimental results show that with a 35 dBFS input sine wave there are no tones above a 110 dB noise floor.

The offset and gain error of ADCs represent two important limits for time-interleaved ADC architectures. The proposed method enables a precise measurement of the offset and the gain during system operation introducing a minimum disturb at the output. The method exploits the modulation of the input signal with a random sequence of +1 and -1. The random bit-stream is generated by using the wide-band output of a time-discrete non-linear circuit. The resulting spread spectrum signal can be easily distinguished by the DC offset and the use of a digital accumulator extracts the offset and the gain of each ADC. The input signal is finally reconstructed, in the digital domain, with a synchronous demodulation. The accumulation time can be as many clock periods (like 106) thus permitting an excellent accuracy in the offset and gain measurement. Simulations of the proposed approach at the behavioral level confirm the effectiveness of the method. It is shown that the offset of a 12-bit ADC can be measured with a 0.1 LSB accuracy

The design of low-power, medium resolution flash converter is presented. The goal is to provide a basic cell with state-of-the art figure of merit thus permitting low-power data converter architectures with a more flexible use of flash ADC cells. The designed 6-bit flash uses interpolation and V/I converters that operate as preamplifier stage of latches. Circuit simulations show a figure of merit as low as 1.2 pj/conv-lev at 100-MS/s sampling frequency and 3.3-V analog supply voltage

This paper proposes a scheme for reducing the maximum swing requirement of the integrator and quantizer in a delta-sigma modulator and discusses its advantages. This technique makes the modulator less sensitive to amplifier non-linearities in the integrator. Moreover, the number of comparators in the multibit quantizer can be greatly reduced since the quantizer only needs to resolve signals with maximum amplitude much less than its own full-scale. Therefore, power and area for the quantizer and loading on the integrator that precedes the quantizer are also reduced. The additional circuitry needed in this scheme can be easily implemented in digital domain.

This paper presents a novel 10-bit pipeline A/D converter for low noise, self-triggered applications. The proposed A/D converter does not require any timing signal (clock) in order to carry out the conversion, assuming that a sampled signal is provided at the input. The circuit basically operates as "combinatorial logic", propagating the partial conversions and the residues through the various stages asynchronously. The presented ADC has been designed in a standard 0.35 mum CMOS technology and the conversion period is lower than 500 ns (i.e. 2 MHz data rate). The power consumption is 39 mW from a 3.3 V power supply. The total chip area without pads is 2.24 mm2

This paper describes a power conversion and data recovery system for a microwave powered sensor platform. A patch microwave antenna, a matching filter and a rectifier make the system frontend and implement the RF-to-DC conversion of power carrier. The efficiency of the power conversion is as high as 47% with an input power level 250 µW at 2.45 GHz. Then, a 0.18 µm CMOS integrated circuit extracts the clock and the digital data. A modified pulse amplitude modulation scheme is used to modulate the data on the 2.45 GHz carrier frequency for combined data and power transmission; this scheme allows very low power consumption of the entire IC to be less than 10 µW and making the system suitable for an autonomous wireless connected sensor module.

Remote sensing technologies have long since been relegated to the implementation of airborne or spaceborne configurations. We recognize that distributed sensors in all configurations can contribute to improved sensor performance and expanded measurement configurations. These new sensor systems require designs that can be scaled to hundreds to potentially thousands of individual sensors or sensor components. This paper describes a novel sensor network design strategy and some suggested operational scenarios. Mega-Mesh sensor networks require special design to support effective communication protocols. There will be a requirement for reliable sensor-to-sensor communication, ad-hoc self organizing network, multiple individual communication network structures, wireless base stations, remotely charging techniques, etc. All of these approaches dictate unique network architectures that eventually interface to conventional communication infrastructure and/or legacy networks.

Design automation for analog/mixed-signal (AIMS) circuits and systems is still lagging behind compared to what has been reached in the digital area. As System-on-Chip (SoC) designs include analog components in most cases, these analog parts become even more a bottleneck in the overall design process. The paper is dedicated to latest R&D activities within the MEDEA+ project ANASTASIA+. Main focus will be the development of seamless top-down design methods for integrated analog and mixed-signal systems and to achieve a high level of automation and reuse in the A/MS design process. These efforts are motivated by the urgent need to close the current gap in the industrial design flow between system specification and design on the one hand and block-level circuit design on the other hand. The paper will focus on three subtopics starting with the top-down design flow with applications from circuit sizing, design centering, and automated behavioral modeling. The next part focuses on modeling and simulation of specific functionalities in sigma-delta design while the last section is dedicated to a mixed-signal System-on-Chip design environment.

Novel low-voltage, low-power techniques in the design of portable wireless communication systems are required. Two system examples of low-power analog multipliers operating from a 1.2 V supply are presented. These proposed structures achieve the required multiplication function by using current processing. The circuits were fabricated using standard double-poly CMOS processes for a 900 MHz application. Measurement results of the prototypes are comparable to other higher voltage designs.

This paper presents a technique for programmable switched-capacitor (SC) filters based on periodical nonuniform individual sampling (PNIS) of each SC structure in the filter. It is shown how very wide range of programmability in all circuit parameters can be obtained, whereas the dynamic range degradation is kept minimum. Experimental results obtained from a 1.2 /spl mu/m CMOS second-order SC filter are given.

A digital-to-analog converter system compliant with the requirements of software radio transmission interfaces is presented. The system, through a proper combination of interpolation, digital filtering and data conversion allows us to relax the speed requirements of the analog and the digital section while fully satisfying the specifications. A design example and high level simulation results are presented.

A low-voltage analog multiplier operating at 1.2V is presented. The multiplier core consists of four MOS transistors operating in the saturation region. The circuit exploits the quadratic relation between current and voltage of the MOS transistor in saturation. The circuit was designed using standard 0.6μm CMOS technology. Simulation results indicate an IP3 of 4.9dBm and a spur free dynamic range of 45dB.

This paper discusses how to apply the approach used in the Chinese Abacus to implement digital arithmetic. Firstly, we examine the representations and the basic techniques used in the Chinese Abacus; then, we propose an MOS realization of the basic functions required; finally, we discuss a novel 12 bit full adder based on the Chinese Abacus method. Simulations of 0.5 /spl mu/m CMOS realizations showed that a parallel solution can run at 200 MHz while a pipeline realization can achieve 1 GHz of clock frequency. The complexity of the circuit is quite limited; thus, the use of the Chinese Abacus approach results in a competitive technique with respect to conventional methodologies.

The design of low-power rail-to-rail output buffers for high capacitive loads is critical. In particular, control of the output current, constant input transconductance and output stage driving must be well confined. In this paper we discuss the major design constraints and present a new topology for a CMOS rail-to-rail output buffer. The experimental results show that the proposed architecture is suitable for input-output signals within the full dynamic.

In this paper we propose an A/D converter for smart sensor read-out systems with limited bandwidth. The system can be associated with various sensors in the case where digital output and high resolution are required. The converter is intended to be cointegrated with IC compatible microsensors. An application of the proposed A/D converter is demonstrated in combination with a two dimensional magnetic vector probe for accurate measurement of the angle of a magnetic field parallel to the chip plane. A two dimensional magnetotransistor serves as sensing element. The converter can be configured to achieve the angle calculation with good accuracy. This system is designed to be used in automotive and drive applications. We successfully implemented the proposed A/D converter in a standard 2 /spl mu/m CMOS technology together with a two dimensional magnetic vector probe.

This paper presents a scheme for an analog monolithic monostable multivibrator suitable for use in a wide variety of applications where a need exists for pulses of a known and precise width in response to a trigger signal. The pulse can be programmed either using a reference current or an external capacitor which allow widths from 5 ns to a maximum which is limited only by capacitor values availability. The circuit was fabricated in a standard 1.2 /spl mu/m BiCMOS technology, but it is shown to be fully CMOS compatible. Measurement results indicate that very high speed is obtained at very low power dissipation and cost.

This paper presents a novel technique for the compensation of the finite gain in active stages used in SC circuits. Simulation results are provided which show a good reduction in both module and phase errors. This technique is a good candidate to be used in high speed SC circuits where the need for a high gain-bandwidth imposes the use of low gain active stages.>

The design of high-accuracy high-frequency comparators needs particular care especially with parameters such as offset and overdrive recovery. This paper discusses the major design constraints and presents a new topology for a CMOS video comparator. The experimental results show that the proposed architecture is suitable for use in high-performance A/D converters.>

In this paper we propose new approach to operate Suppressed Sidewall Injection dual collector Magnetotransistor (SSIMT), which allows one to reduce the power consumption and to implement directly switched capacitor signal-processing functions. This is obtained using charge instead of current to drive the device. Because of the clocked operation, the static power dissipation is eliminated and a sampled signal is obtained directly from the sensor. The proposed approach has been experimentally verified and the obtained results are presented.>

A software tool named TOSCA (Tool for Oversampled Switched-Capacitor A/D Converter Analysis) is described. The simulator is behavioral, general purpose and fully user-friendly. Because a set of basic building blocks is available, generic switched-capacitor noise-shaping A/D converters can be analyzed simply by building netlist file. Two hierarchical levels have been considered for circuit description: block level for subcircuits like quantizers and digital filters, and component level for subcircuits like the integrators where switches, capacitors and operational amplifiers are used as building elements. The developed models allow the most relevant nonideal parameters of the components to be taken into account, and a set of postprocessing facilities allows extensive analysis of the circuits. The program is written in C language, uses dynamic memory allocation, and is very fast.>

The authors present a modified direct-digital synthesizer which uses noise shaping to reduce the effects of phase-accumulator truncation on the output spectrum. The discrete spectral disturbances associated with this truncation error are strongly reduced with the proposed method, making the synthesizer suitable for high-performance signal processing. The proposed architecture uses first-order noise shaping. Higher order noise shaping can also be used if required. The modified circuit offers considerable improvement in the synthesizer performance when the generated frequency is low with respect to the clock frequency.>

A circuit is described which uses one oversampling frequency synthesizer in an interleaved mode to generate dual-tone multifrequency (DTMF) telephone dialing tones. The synthesizer is based on direct digital synthesis using phase accumulation. The digital-to-analog conversion is carried out using a first-order sigma-delta converter. This sigma-delta converter requires only a simple second-order RC filter, eliminating the need for a switched capacitor filter. Measurements on the circuit confirm that all specifications of the DTMF are fulfilled.>