In this paper we present the new version of a multi-context reconfigurable datapath called PiCoGA (pipelined configurable gate array). The device provides a clear interface model and can be easily embedded in SoC systems where low power consumption and high computation capability are required. New logic cells and routing architecture have been designed for an efficient implementation of computation-intensive algorithms. The integration of a dedicated control unit for pipeline activity control provides a dataflow computational model which is easy to be integrated in a SoC. The embedded datapath has been designed using a 0.13 /spl mu/m CMOS technology. The implementation of several functions in the datapath achieves an average gate density of 1.3 KGates/mm/sup 2/ for each of the four available contexts.

Reconfigurable architectures are well suited for wireless applications since they provide high performance computation together with the capability to adapt to changing communication protocols. Moving to 90nm technology and below, FPGAs could suffer from leakage energy consumption due to the large number of inactive transistors. We propose to combine super cut-off, body biasing and multi-threshold techniques to reduce the leakage current of programmable interconnections, which give by far the main contribution to static power dissipation. Super cut-off (gate biasing) technique is well suited for high-speed pass-transistors, while body biasing can be adopted for large buffers. On the other hand high threshold transistors can be used where delays are not critical. We show the design of SRAM cells generating the required high swing signals for gate-biased and body-biased transistors without affecting transistor reliability. Compared to a standard design the adoption of a mixed technique reduces routing leakage by more than one order of magnitude with only a 5% increase in switch delay and a 9% in tile area, while with respect to a full dual-threshold approach, delay is reduced by 23%.

Multi-context FPGAs are a convenient solution for run-time reconfiguration, but they suffer from large area occupation. This is mainly due to programmable interconnect configuration memories which need to be replicated as many times as the number of contexts. This limitation can be overcome with a DBM (Decoder Based Multicontext) routing architecture which introduces a decoding stage between configuration memories and routing structures, so that the number of SRAM cells can be highly reduced. Both the switch and connect blocks have been designed, at the architectural and schematic level. A suitable router for DBM structures has also been developed. The results show that the approach adopted requires on average only 5% more tracks whereas the device area occupation is reduced up to 40%. We also show that DBM routing architecture does not affect the critical path delay, due to the reduction of the routing wire length.