Demo Data from EDBT 2026 / reviewers in the wild / expert
William M. van Cleemput
dblp:21/5157
· DBLP profile ↗
15ranked-venue papers
5as first author
0since 2021 · last 1994
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 15 · 5 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
14 papers |
Electronic design automation · 88% Processor architecture and microarchitecture · 4% Performance modeling and evaluation · 3% |
Topics — the 24 heaviest of 27, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 6 | 1982 | Automated partitioning of hierarchically specified digital systems · DAC 1982 Optimal Layout of CMOS Functional Arrays · IEEE Trans. Computers 1981 Optimal layout of CMOS functional arrays · DAC 1979 |
Electronic design automation
logic synthesis |
0.0 | 2 | 1981 | Optimal Layout of CMOS Functional Arrays · IEEE Trans. Computers 1981 Automatic PLA synthesis from a DDL-P description · DAC 1981 |
Electronic design automation
hardware description language |
0.0 | 2 | 1979 | Computer hardware description languages and their applications · DAC 1979 An hierarchical language for the structural description of digital systems · DAC 1977 |
Electronic design automation › physical design
circuit partitioning |
0.0 | 1 | 1982 | Automated partitioning of hierarchically specified digital systems · DAC 1982 |
Electronic design automation › design methodology
hierarchical design |
0.0 | 1 | 1982 | Automated partitioning of hierarchically specified digital systems · DAC 1982 |
Electronic design automation › physical design
cell layout |
0.0 | 1 | 1981 | Optimal Layout of CMOS Functional Arrays · IEEE Trans. Computers 1981 |
Electronic design automation › design automation tools
parallel electronic design automation |
0.0 | 1 | 1981 | A parallel bit map processor architecture for DA algorithms · DAC 1981 |
Electronic design automation › logic synthesis › programmable logic array
programmable logic array design |
0.0 | 1 | 1981 | Automatic PLA synthesis from a DDL-P description · DAC 1981 |
Electronic design automation › hardware verification and test
functional verification |
0.0 | 1 | 1980 | Developments in verification of design correctness (A Tutorial) · DAC 1980 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 1980 | Developments in verification of design correctness (A Tutorial) · DAC 1980 |
Electronic design automation › physical design
printed circuit board design |
0.0 | 2 | 1979 | Implementation of an interactive printed circuit design system · DAC 1978 Dynamic design rule checking in an interactive printed circuit editor · DAC 1979 |
Electronic design automation › hardware verification and test › formal verification
symbolic simulation |
0.0 | 1 | 1980 | Developments in verification of design correctness (A Tutorial) · DAC 1980 |
Electronic design automation › physical design › layout verification
design rule checking |
0.0 | 1 | 1979 | Dynamic design rule checking in an interactive printed circuit editor · DAC 1979 |
Electronic design automation › hardware simulation
multilevel simulation |
0.0 | 1 | 1979 | SABLE: A tool for generating structured, multi-level simulations · DAC 1979 |
Electronic design automation › physical design
placement |
0.0 | 1 | 1979 | Placement algorithms for arbitrarily shaped blocks · DAC 1979 |
Performance modeling and evaluation
simulation |
0.0 | 1 | 1979 | SABLE: A tool for generating structured, multi-level simulations · DAC 1979 |
Electronic design automation › CAD framework
interactive design environment |
0.0 | 1 | 1978 | Implementation of an interactive printed circuit design system · DAC 1978 |
Electronic design automation › hardware description language
structural description language |
0.0 | 1 | 1977 | An hierarchical language for the structural description of digital systems · DAC 1977 |
Electronic design automation › physical design
VLSI layout |
0.0 | 1 | 1976 | On the topological aspects of the circuit layout problem · DAC 1976 |
Reconfigurable computing and FPGAs › reconfigurable architecture
reconfigurable logic |
0.0 | 1 | 1981 | Automatic PLA synthesis from a DDL-P description · DAC 1981 |
Integrated circuit design › semiconductor device fabrication
CMOS technology |
0.0 | 1 | 1979 | Optimal layout of CMOS functional arrays · DAC 1979 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1979 | Optimal layout of CMOS functional arrays · DAC 1979 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1979 | SABLE: A tool for generating structured, multi-level simulations · DAC 1979 |
Electronic design automation › hardware verification and test › functional verification
simulation-based verification |
0.0 | 1 | 1979 | SABLE: A tool for generating structured, multi-level simulations · DAC 1979 |
Methods — techniques the papers use, named apart from their topics
iterative improvement · 0.0heuristic partitioning · 0.0graph-theoretical algorithm · 0.0topological layout procedure · 0.0placement algorithm · 0.0interactive design · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1994 | Software Patents and Their Potential Impact on the EDA Community (Panel)abstractNo abstract available. William M. van Cleemput, Ewald Detjens, Herman Beke, George C. Chen, Joseph Hustein, William Lattin, Dennis S. Fernandez |
DAC | 1 |
| 1982 | Automated partitioning of hierarchically specified digital systemsabstractThis paper describes a heuristic algorithm for automatically partitioning digital systems. High- level information contained within a hierarchical design is used to increase the effectiveness of this algorithm. This algorithm uses a constructive process to build a physical design of a hierarchically specified logic design. An iterative improvement step is then done. Thomas S. Payne, William M. van Cleemput |
DAC | 2 |
| 1981 | A parallel bit map processor architecture for DA algorithms
Tom Blank, Mark Stefik, William M. van Cleemput |
DAC | 3 |
| 1981 | Automatic PLA synthesis from a DDL-P description
William M. van Cleemput |
DAC | 2 |
| 1981 | Optimal Layout of CMOS Functional ArraysabstractDesigners of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design automation systems. Takao Uehara, William M. van Cleemput |
IEEE Trans. Computers | 2 |
| 1980 | Developments in verification of design correctness (A Tutorial)abstractThis paper reviews recent developments in the verification of digital systems designs. The emphasis is on proof of functional correctness. Some of the techniques reviewed are symbolic simulation (including parallel simulation of HDL descriptions), dataflow verification by grammar construction, comparison of manually generated design with automated design, and functional abstraction. Wendell E. Cory, William M. van Cleemput |
DAC | 2 |
| 1979 | Dynamic design rule checking in an interactive printed circuit editor
Tom C. Bennett, Kim R. Stevens, William M. van Cleemput |
DAC | 3 |
| 1979 | Computer hardware description languages and their applications
William M. van Cleemput |
DAC | 1 |
| 1979 | SABLE: A tool for generating structured, multi-level simulations
Dwight D. Hill, William M. van Cleemput |
DAC | 2 |
| 1979 | Placement algorithms for arbitrarily shaped blocks
Bryan Preas, William M. van Cleemput |
DAC | 2 |
| 1979 | Optimal layout of CMOS functional arrays
Takao Uehara, William M. van Cleemput |
DAC | 2 |
| 1978 | Implementation of an interactive printed circuit design system
Kim R. Stevens, William M. van Cleemput, Tom C. Bennett, Jon A. Hupp |
DAC | 2 |
| 1977 | An hierarchical language for the structural description of digital systems
William M. van Cleemput |
DAC | 1 |
| 1976 | On the topological aspects of the circuit layout problemabstractThis paper investigates the topological and geometrical characteristics of the circuit layout problem. A topological layout procedure is presented. This procedure can be especially useful for integrated circuit layout. William M. van Cleemput |
DAC | 1 |
| 1975 | On the status of design automation in canada
William M. van Cleemput, R. F. Allum, James G. Linders |
DAC | 1 |