We can classify multi-FPGA prototyping platforms in three categories: hardwired off-the-shelf, cabling and custom. Three points are developed in this paper. Firstly, an automatic design flow is proposed to generate a cabling platform and a custom platform for a given design. Then, the optimal width of cables for a cabling multi-FPGA platform is explored. Finally, the performances of these three multi-FPGA platforms are compared. The results show that the cabling platform achieves up to 82% gain in performance, and the custom platform achieves up to 100%, compared to the hardwired off-the-shelf platform. The custom platform achieves up to 20% gain in performance over the cabling platform. Therefore the results show that, apart from some stringent constraints (such as deployment cost or specific frequency needed), the relatively new cabling paradigm with the proposed automatic, inter-FPGA tracks distribution tool, offers an attractive alternative compared to the two other platforms.

Multi-FPGA boards are widely used for rapid system prototyping. Even though the prototyping is trying to reach the maximum performance, the performance is limited by the inter-FPGA communication. As the capacity per I/O for each FPGA generation is increasing, FPGA I/Os are becoming a scarce resource. The design is divided into several parts, each part's capacity fits in a single FPGA. Signals crossing design's parts located in different FPGAs are called cut nets. In order to resolve pin limitation problem, cut nets are sent between FPGAs in pipelined way using the Time-Division-Multiplexing technique. The maximum number of cut nets passing through one FPGA I/O is called the TDM ratio. There are two multiplexing architectures used for multi-FPGA based prototyping: Logic Multiplexing and ISERDES/OSERDES. In this paper, a new multiplexing architecture Multi-Gigabit Transceiver (MGT) is proposed. Experiments are done in a multi-FPGA board with the testbench LFSR to validate the achieved performance. Assume that all the FPGA I/Os used for inter-FPGA communication are MGT capable in the future. Analyses show that the proposed multiplexing architecture can achieve higher performance when the TDM ratio exceeds 67. The gain in performance of the proposed architecture over the existing architecture augments as the TDM ratio increases.

Multi-FPGA boards suffer from large timing delays in inter-FPGA physical tracks compared to intra-FPGA track delays, as well as a limited bandwidth between FPGAs due to the limited number of I/Os per FPGA. In order to tackle this problem, an algorithm which routes multi-terminal nets in multi-point tracks is proposed in this paper to spare FPGA I/Os. Experiments are conducted using Gaisler Research Benchmarks. Firstly, each testbench will be implemented in an off-the-shelf board. The results show that the system frequency can be increased in the off-the-shelf board by the proposed routing algorithm. Secondly, an automatic design flow which generates a custom multi-FPGA board is enhanced by generating multi-point tracks in the board, and each testbench will be implemented with the proposed routing algorithm in custom boards. The results show that the system frequency is improved in the custom board with both 2- and multi-point tracks.

Reaching a physical limitation in terms of power consumption, the new chosen axis to increase the performance is to scale the number of processing elements (PEs) instead of increasing the speed of processors. These complex systems often take the form of a Multi-Core System-on-Chip (MCSoC) in which individual nodes are connected using a Network-on-Chip (NoC). FPGA-based prototyping is no longer optional to test these very large designs. A multi-FPGA prototyping board, which is a collection of FPGAs, is used when the logic capacity of a single FPGA is insufficient. Nevertheless, multi-FPGA boards come with some constraints, which lower the system frequency. However, cluster-based MCSoCs have a great value: their flexibility in terms of form factor. In this paper, a parameterizable cluster-based MCSoC with a mesh topology has been designed. An indicator based on the average Rent's Rule of cluster-based MCSoCs has been proposed to predict the best form factor in order to obtain the maximum prototyping system frequency. The targeted prototyping platform is a six Virtex-5 multi-FPGA board. The results show that for a given total number of PEs in cluster-based MCSoCs, a lower indicator can result in a higher system frequency.

In SoC designs, limited test access to internal cores, low-cost external tester's lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore, this paper presents an embedded micro-tester for testing IEEE1500-compliant SoCs. In the proposed approach, the test program is no more executed by the external tester but by the embedded micro-tester. Under the control of the embedded SoC microprocessor, the micro-tester executes the test programs stored outside of the SoC in an external memory. The micro-tester supports stuck-at testing as well as both at-speed testing techniques: launch-on-last-shift (LOLS) and launch-on-capture (LOC). Using the ITC'02 benchmarks, experimental results are presented: test application time, test data volume and area overhead

This paper presents STEPS, an innovative software-based approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator applying vectors to the SoC test pins but rather as a target, a huge repository of 32-bits test data and control commands. The ATE is connected to the functional SoC external RAM controller interface. The only additional test component in the SoC is a P1500 test processor that converts test data into serial P1500 streams. This paper applies the STEPS methodology to SoCs containing a VCI-compliant interconnect, a microprocessor, P1500-compliant IP cores and an external RAM controller interface. Using the ITC02 SoC benchmarks, a comparison is done between the STEPS architecture and a classical bus-based strategy.