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Wen-Yen Tsai

dblp:21/5692 · DBLP profile ↗
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6ranked-venue papers
2as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 3 · 2 first-authorArtificial intelligence and machine learning · 1Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 50% Parallel and multicore computing · 50%
Computer networks
1 paper
Internet architecture and protocols · 50% Software-defined and programmable networks · 50%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel architecture
multicore packet processing
0.212016
qcAffin: A Hardware Topology Aware Interrupt Affinitizing and Balancing Scheme for Multi-Core and Multi-Queue Packet Processing Systems · IEEE Trans. Parallel Distributed Syst. 2016
Performance modeling and evaluation
workload characterization
0.212016
qcAffin: A Hardware Topology Aware Interrupt Affinitizing and Balancing Scheme for Multi-Core and Multi-Queue Packet Processing Systems · IEEE Trans. Parallel Distributed Syst. 2016
Software-defined and programmable networks › programmable data plane
deep packet inspection
0.112016
qcAffin: A Hardware Topology Aware Interrupt Affinitizing and Balancing Scheme for Multi-Core and Multi-Queue Packet Processing Systems · IEEE Trans. Parallel Distributed Syst. 2016
Internet architecture and protocols
packet processing
0.112016
qcAffin: A Hardware Topology Aware Interrupt Affinitizing and Balancing Scheme for Multi-Core and Multi-Queue Packet Processing Systems · IEEE Trans. Parallel Distributed Syst. 2016

Methods — techniques the papers use, named apart from their topics

numerical cost model · 0.5dynamic load balancing · 0.5
YearPublicationVenuePosition
2016 qcAffin: A Hardware Topology Aware Interrupt Affinitizing and Balancing Scheme for Multi-Core and Multi-Queue Packet Processing Systems
abstract
Interrupt affinitization of multi-queue network interface cards is a fundamental composition that defines how packets from individual queue are processed by which CPU-cores on multi-core platforms. In this paper, we propose qcAffin to attain an optimal queue-to-core affinitization for packet processing systems based on a numerical cost model derived from hardware topology and runtime system workloads. Static architectural characteristics comprising the memory hierarchy and topology of hardware components are first analyzed to calculate static interrupt affinitization costs. Then we attempt dynamic interrupt affinitization to balance workloads on CPU-cores and improve overall performance. Classical networking applications ranging from bridging, routing, access control list (ACL) matching to deep packet inspection (DPI) with different frame sizes are extensively experimented to compare the performance of the proposed scheme and other existing approaches. As demonstrated in the comparison result, qcAffin achieves the similar performance of the best affinitization approach and outperforms the Linux default affinitizer by averages of 102, 278, 248 and 131 percent on 1G NICs for the four applications. On 10G NICs, dramatic boosts of 1,424 and 1,343 percent are measured for the bridging and routing applications, respectively. Moreover, the effectiveness of dynamic interrupt balancing is justified by a maximum of 150 percent higher system utilization and 1.2 Mpps more throughput compared to the fixed affinitization approach in a simulated setup of unbalanced traffic load.
Nen-Fu Huang, Wen-Yen Tsai
IEEE Trans. Parallel Distributed Syst.2
2012 A unique-pattern based pre-filtering method for rule matching of network security
abstract
As a result of continually changing Internet and applications, more and more advanced features are requested to be available in the appliance for more accurately monitoring and managing the network. Therefore, modern networking appliances are equipped with the DPI (Deep Packet Inspection) technology to scan the payload of a packet. A rule (like Snort rules) may consist of several patterns with certain relationships, such as order, relative positions, and offset, etc. The system performance is usually dominated by not only the pattern matching algorithm but also the rule match processing algorithm. This paper proposes a unique-pattern based pre-filtering method for the rule matching. It is employed to filter out unwanted matches after scanning the packet payload by the pattern matching algorithm. The proposed algorithm is also implemented on different multi-core platforms to demonstrate its efficiency and performance. The experimental results indicate that the throughput is improved significantly and can be increased approximately linearly to the number of CPU cores.
Nen-Fu Huang, Hsien-Wei Hung, Wen-Yen Tsai
APCC3
2012 A port-configuration assisted NIC IRQ affinitization scheme for multi-core packet forwarding applications
abstract
Interrupt affinitization of network interface cards (NICs) is a fundamental composition that defines how packets are processed by which CPU-cores on multi-core platforms. In this paper, we propose a simple port-configuration assisted scheme to attain an optimal affinitization for packet forwarding applications. Experiments ranging from bridging, routing, flow tracking to deep packet inspection are conducted to show the performance impacts utilizing different affinitization approaches. As a result, our proposed scheme achieves the same performance level as the best fixed affinitization scheme. In addition, the effectiveness of interrupt balancing is demonstrated for our scheme to be superior to the widely-deployed irqbalance with varying network settings.
Wen-Yen Tsai, Nen-Fu Huang, Hsien-Wei Hung
GLOBECOM1
2011 A Lock-Controlled Session Table Partitioning Scheme with Dynamic Resource Balancing for Multi-Core Architecture
abstract
Connection tracking by manipulating session tables is essential for stateful inspection capable applications such as stateful firewalls, network-based intrusion prevention systems (NIPS), traffic accounting and monitoring to process packets according to session state information. With the prevalence of multi-core computing, it is crucial to optimize the existing connection tracking structures and algorithms to fully utilize the underlying parallelism. In this paper, we propose a lock-controlled session table partitioning scheme accompanied with a dynamic resource balancing algorithm for session-aware multi-core networking systems. Experimental results show that the proposed scheme reduces the number of lock contentions to a maximum of 100 times less and, in turn, boosts the performance to 3.5 Gbps higher than the baseline. 100% resource utilization is also achieved by overcoming the constraint of fixed-sized partitioning.
Wen-Yen Tsai, Nen-Fu Huang, Hsien-Wei Hung
ICC1
2010 SHOCK: A Worst-Case Ensured Sub-Linear Time Pattern Matching Algorithm for Inline Anti-Virus Scanning
abstract
To detect viruses, worms and, malware in the multi- gigabit environment, it is crucial for modern content-aware network security appliances to have a fast virus scanning scheme.Signature based multi- pattern matching algorithm is the core technology to enable fast virus scanning accurately and quickly. This paper proposes a multi-pattern matching algorithm with a simple shift/hash technique and a novel heuristic by inspecting overlaps between pairs of patterns to ensure both average and worst-case performance. Experimental results show that our algorithm performs 600 Mbps to 1.4 Gbps faster than the ClamAV AC and BM-based algorithms and achieves a maximum of 3.8 Gbps throughput in inline virus scanning while the memory consumption is nearly the same.
Nen-Fu Huang, Wen-Yen Tsai
ICC2
2003 An Experimental Study of Model Predictive Control Based on Artificial Neural Networks
Ji-Zheng Chu, Po-Feng Tsai, Wen-Yen Tsai, Shi-Shang Jang, David Shan-Hill Wong, Shyan-Shu Shieh, Pin-Ho Lin, Shi-Jer Jiang
KES3