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Javier Rodríguez

dblp:21/5924 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2015
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Performance modeling and evaluation · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › timing analysis
statistical timing analysis
0.212014
Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
Electronic design automation
timing analysis
0.212014
Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
Electronic design automation › timing analysis
transistor-level timing analysis
0.212014
Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
Performance modeling and evaluation › simulation
monte carlo simulation
0.112014
Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014

Methods — techniques the papers use, named apart from their topics

transistor-level gate models · 0.2random differential equation solver · 0.2current source models · 0.2
YearPublicationVenuePosition
2015 Generating native user interfaces for multiple devices by means of model transformation
abstract
In the last years, the types of devices used to access information systems have notably increased using different operating systems, screen sizes, interaction mechanisms, and software features. This device fragmentation is an important issue to tackle when developing native mobile service front-end applications. To address this issue, we propose the generation of native user interfaces (UIs) by means of model transformations, following the modelbased user interface (MBUI) paradigm. The resulting MBUI framework, called LIZARD, generates applications for multiple target platforms. LIZARD allows the definition of applications at a high level of abstraction, and applies model transformations to generate the target native UI considering the specific features of target platforms. The generated applications follow the UI design guidelines and the architectural and design patterns specified by the corresponding operating system manufacturer. The objective is not to generate generic applications following the lowest-common-denominator approach, but to follow the particular guidelines specified for each target device. We present an example application modeled in LIZARD, generating different UIs for Windows Phone and two types of Android devices (smartphones and tablets).
Ignacio Marín 0002, Francisco Ortin, German Pedrosa, Javier Rodríguez
Frontiers Inf. Technol. Electron. Eng.4
2014 Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver
abstract
To improve the accuracy of static timing analysis, the traditional nonlinear delay models are increasingly replaced by more physical gate models, such as current source models and transistor-level gate models. However, the extension of these accurate gate models for statistical timing analysis is still challenging. In this paper, we propose a novel statistical timing analysis method based on transistor-level gate models. The accuracy and efficiency are obtained by using an efficient random differential equation based solver. The correlations among signals and between input signals and delay are fully accounted for. In contrast to Monte Carlo simulation solutions, the variational waveforms for statistical delay calculation are obtained by simulating only once. At the end of statistical timing analysis, both the statistical delay moments and the variational waveforms are available. The proposed algorithm is verified with standard cells and ISCAS85 benchmark circuits in a 45-nm technology. The experimental results indicate that the proposed method can capture multiple input simultaneous switching for statistical delay calculation, and can provide 0.5% error for delay mean and 2.7% error for delay standard deviation estimation on average. The proposed statistical simulation introduces a small runtime overhead with respect to static timing analysis runtime. The MATLAB implementation of the proposed algorithm has two orders of magnitude speedup, compared to Spectre Monte Carlo simulation.
Javier Rodríguez, Amir Zjajo, Michel Berkelaar, N. P. van der Meijs
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2