This article introduces a digital conversion and linearization unit (DCLU) that performs signal conversion and power amplifier (PA) linearization when the digital-to-analog converter (DAC) is constrained by limited bit resolution. The proposed structure applies an error-and-distortion-feedback (EDF) processing principle that integrates re-quantization, noise shaping, and digital predistortion (DPD) within a single digital unit and avoids explicit inverse modeling. The embedded PA forward description uses a polar look-up table (PLUT) representation of the PA static AM/AM and AM/PM characteristics and a linear filter that captures the measured dynamic response. More advanced approaches are also described in terms of incorporating more elaborate forward models within the DCLU, together with a parallel multi-channel realization that relaxes internal clock-rate requirements through time-interleaved processing. The concept is validated through two RF measurement experiments using a 5G New Radio (NR) transmit waveform at 3.5 GHz and 3.6 GHz (NR band n78). The first experiment uses a broadband Gallium-Nitride (GaN) HMC1114 PA to demonstrate the proof of concept and quantify system behavior under reduced bit resolutions. The second experiment uses the Qorvo QPA3503 GaN Doherty PA to evaluate the approach for an amplifier type that is typically more challenging to linearize. The measured results show that the proposed approach maintains good linearization capability under reduced bit resolutions and, in the reported cases, provides improved transmit waveform quality relative to conventional reference DPD schemes, particularly at lower bit widths.

This paper proposes a semi-supervised quantum particle swarm optimization-based tone reservation (SS-QPSO-TR) method with affinity propagation (AP) clustering and k-nearest neighbours (KNN) algorithms. The proposed SS-QPSO-TR method reduces the high peak-to-average power ratio (PAPR) in orthogonal time sequency multiplexing (OTSM) systems. The main finding is a significant 4.5 dB, 4.3 dB and 4 dB PAPR reduction in contrast to the original OTSM for QAM-64, 16 and 4, respectively while concurrently reducing transmission computational complexity by 16.7 times, compared to adapted tone reservation in both-domain (A-TR-BD), at the same bit error rate (BER) and error vector magnitude (EVM) performance. The proposed SS-QPSO-TR scheme enables efficient modulation of OTSM transmitters in high-mobility, real-time, wireless communication scenarios.

The paper presents a comprehensive theoretical analysis of dual-input digital Doherty power amplifiers (DPAs) and outlines a specific design methodology. The theory explains how adaptive input signals affect the linearity and efficiency of the amplifiers, as well as the necessary adjustments to the operating point of the peaking amplifier. Using the analytical model, the paper offers guidance on adjusting the input signal to achieve the highest efficiency, ensuring that the carrier amplifier remains in saturation mode within the load-modulated region. It also discusses the maximum theoretically achievable efficiency for digital DPAs, which serves as a benchmark for comparing results with other amplifier topologies. Additionally, the paper proposes a practical approach for implementing the adaptive input algorithm during the measurement of modulated test signals. This method combines the measured response of the DPA with the theoretically derived optimal input signal splitting pattern, creating test signals for both the carrier and peaking input paths of the DPA. This effectively addresses unseen sources of nonlinearity by the theoretical model within the input signal bandwidth. Validation experiments were conducted on a 50W dual-input DPA designed for 5G wireless communication at 3.5 GHz, utilizing a 90 MHz modulated signal.

In recent years, fully-connected hybrid beamforming (FC-HBF) architecture has aroused widespread interest for millimeter wave (mmWave) massive multi-input multi-output (MIMO) communication systems. However, the FC-HBF structure suffers from significant linearity deterioration, limiting its applications in actual mmWave transmitters. To resolve this issue, an effective digital predistortion (DPD) method utilizing analytical multi-input behavioral models is proposed in this paper for linearizing the FC-HBF system. Based on the nonlinearity analysis and behavioral modeling of the array response, three analytical multi-input models are derived by embedding the priori beamforming information in the predistorter. The complexity of the proposed analytical models is significantly reduced compared to the state-of-the-art. Numerical simulations and experimental measurement are carried out on a$4\times 64$mmWave FC-HBF array and$2\times 16$quasi-test platform respectively to validate the performance of the proposed DPDs against the state-of-the-art DPDs, which show significant linearization abilities to compensate for the nonlinear distortions of beam signals. The proof-of-the-concept validations in this paper indicate that the proposed scheme is fully capable of linearizing an mmWave FC-HBF array.

In this paper, focusing on the power amplifier (PA) in ultra low power RF circuits and systems, a novel circuit topology with active second harmonic injection technique is derived and analyzed for the wideband high-efficiency continuous class-F/F-1(CCF/F-1) modes for the first time. By introducing an auxiliary PA operated at the second harmonic frequency of the desired band, the optimal phase shift parameter between the drain voltage and current of the CCF/F-1PA can be selected properly, leading to the improvement of the total efficiency and output power. Calculated results show that, with the proposed structure, the maximum output powers are 1.323 and 1.319 times larger than those in the traditional CCF and CCF-1modes, and the maximum drain efficiencies are increased to 98.16% and 93.16%, respectively. Finally, in order to verify the validity of the proposed circuit, a frequency-domain simulation has been presented. It is shown that the difference of intrinsic voltage and current waveforms, drain efficiency as well as output power between the results of theory and simulation is very small.

This article presents an ultra-broadband distributed efficient power amplifier (DEPA) with reactance compensation and adaptive biasing. It is illustrated that the bandwidth of the DEPA can be improved apparently by applying a shunt short-circuited stub at the combining point. The principle of such method is that the back-off impedance variation with frequency can be compensated by the reactance of the shunt stub. Besides, to get over the high gain compression of the conventional DEPA, an adaptive biasing scheme is proposed for the auxiliary PAs. A DEPA is implemented in a 0.25-$\mu \text{m}$GaN-HEMT process for validation. The shunt stub is realized by a LC tank equivalently for a compact size. The fabricated DEPA achieves a saturated output power of 41.5–43 dBm and an 8-dB back-off drain efficiency (DE) of 38%–46.8% from 1.8 to 5.4 GHz with a chip size of$3.2\times3.2$mm2. The fractional bandwidth (FBW) is up to 100%. Applying a 100-MHz LTE signal with an 8.5-dB peak-to-average power ratio (PAPR), an average DE of 35%–43% is measured over the entire bandwidth, and adjacent channel power ratio (ACPR) is better than −47 dBc after applying digital predistortion. To the best of our knowledge, the proposed DEPA demonstrates the largest FBW among all reported integrated back-off efficient PAs without using digital techniques or reconfiguration.

This article presents a 24–40-GHz broadband beamforming transmit–receive (T/R) front-end (FE) chip for the next-generation millimeter-wave (mm-wave) communication systems. To achieve multiband coverage in a single beamforming front-end IC, the proposed beamforming chip adopts a unified gain and phase control scheme as well as an asymmetric T/R switch circuit, which simplifies the system design and enables broadband operation in both directions. The vector-modulation-based unified phase and gain control (UPGC) scheme eliminates the standalone variable gain amplifier (VGA) in the front end. The bidirectional impedance transformation T/R switch reduces the insertion loss in the TX path and enables Class-F$^{-1}$operation to improve the bandwidth and efficiency. Based on the proposed UPGC scheme and T/R switch circuit, a high-performance mm-wave front-end chip is implemented using a 0.13-$\mu$m SiGe BiCMOS technology. The fabricated front-end chip achieves 12.9–16.9-dBm maximum output power in TX mode, up to 14.3-dB gain and 7.4–9.2-dB noise figure (NF) in RX mode over the frequency range of 24–40 GHz. In both TX and RX modes, the proposed chip achieved less than 0.4-dB rms gain error and 2.0$^{\circ}$rms phase error. A four-element dual-band phased array module is designed and tested to evaluate the performance of the proposed chip in the 28-and 38-GHz dual-band phased array.

In this article, we propose a new robust and highly efficient digital predistortion (DPD) concept for the linearization of wideband RF power amplifiers (PAs). The proposed approach is based on the combination of a parallelized delta-sigma modulator (DSM) and a forward model of the PA. This concept applies multi-rate techniques on a DSM that incorporates the forward PA model in its feedback loop to perform the required signal predistortion. Such a technique eliminates the need of reverse modeling and its associated problems. The multi-rate approach relaxes enormously the clock speed requirement of the DPD, which allows handling high signal bandwidths at feasible sampling rates. Moreover, enhanced performance can be achieved without the need of increasing the order of the modulator which reduces the sensitivity of the system to gain variations and phase distortions caused by the nonlinear PA characteristics. Three time-interleaved parallel DPD (P-DPD) variants are described and introduced, all of them have been shown to offer increased accuracy, and consequently better linearization performance compared to the DSM-based DPD state-of-the-art. The proposed architectures are tested and assessed using extensive real-world RF measurements at the 3.6 GHz band utilizing wideband 100 MHz 5G New Radio (NR) transmit waveforms, evidencing excellent transmit signal quality.

In this paper, a low complexity moving average nested generalized memory polynomial model (MAN-GMP) is proposed for digital predistortion (DPD) of broadband power amplifiers (PAs). As the signal bandwidth increases drastically, the strong nonlinear distortions, especially those induced by the memory effect, are generated from the highly efficient PAs. To compensate for the strong memory effect, a moving average nested envelope memory polynomial (MAN-EMP) model is derived from an accuracy-enhanced GMP model, which offers reduced complexity while suffering from degraded modeling accuracy. The MAN-GMP model is further proposed to improve the modeling accuracy by connecting several memory branches of the MAN-EMP model in parallel. An iterative algorithm is designed to extract the model coefficients efficiently through only one or two iterations. Experimental measurements are carried out on two sub-7 GHz broadband GaN Doherty PAs with up to 200 MHz bandwidth OFDM signals to benchmark the proposed MAN-GMP model against the GMP, the parallel-LUT-MP-EMP (PLUME), the augmented complexity-reduced GMP (ACR-GMP), the generalized twin-nonlinear two-box (GTNTB), and the enhanced Wiener models. The experimental results show that the MAN-GMP model can effectively compensate for the nonlinear distortion of broadband PAs with significant complexity reduction.

This article proposes a broadband high-efficiency parallel-circuit (PC) class-EF power amplifier (PA) along with a quarter-wavelength stub for the first time. By adding a reactive element${X}$, the design space is expanded so that the impedance terminations of the fundamental and harmonics are no longer fixed points. Based on the broadband capability of the proposed structure, using a GaN HEMT transistor, a proof-of-concept circuit implemented with the Chebyshev impedance transformation network is designed and fabricated. Experimental results demonstrate a high-efficiency broadband PA operating from 2.6-3.9 GHz, with the average efficiency of 71.5%, the measured output power (${P}_{\textit {out}}$) of 38.8-40.9 dBm and the power gain of 8.5-10.6 dB.

This article presents two novel digital predistortion (DPD) based architectures that jointly mitigate the inphase/quadrature (IQ) modulator impairments and the power amplifier (PA) nonlinear distortion in wireless transmitters. The proposed architectures are multibit cartesian and complex delta-sigma modulator-based joint DPDs, called CDSM-JDPD and CXDSM-JDPD, respectively, which enable using low-cost digital-to-analog converters (DACs) while offering versatile linearization capabilities to combat the coexisting distortions of the PA and the IQ modulator. The proposed approach alleviates the need for reverse modeling and implementation of extra hardware to separately deal with frequency-dependent IQ impairments. Moreover, the CXDSM-JDPD enhances the linearization performance and relaxes the high oversampling ratio (OSR) requirement by quantizing the signal more efficiently. Furthermore, the presented concepts inherently support the use of low-resolution DACs, which offers a tremendous advantage in designing and implementing low-cost and energy-efficient radio transmitters. Extensive set of hardware-in-the-loop RF verification measurements with a commercial PA are provided, including two timely 5G New Radio (NR) scenarios at NR bands n3 and n78, while covering channel bandwidths up to 100 MHz and varying the OSR and the DAC bit resolution. The obtained results demonstrate the excellent linearization capabilities of the proposed solutions and their superiority compared to other DSM-based DPD approaches.

Power amplifier (PA) models, such as the neural network (NN) models and the multilayer NN models, have problems with high complexity. In this article, we first propose a novel behavior model for wideband PAs, using a real-valued time-delay convolutional NN (RVTDCNN). The input data of the model is sorted and arranged as a graph composed of the in-phase and quadrature ( I/Q ) components and envelope-dependent terms of current and past signals. Then, we created a predesigned filter using the convolutional layer to extract the basis functions required for the PA forward or reverse modeling. Finally, the generated rich basis functions are input into a simple, fully connected layer to build the model. Due to the weight sharing characteristics of the convolutional model's structure, the strong memory effect does not lead to a significant increase in the complexity of the model. Meanwhile, the extraction effect of the predesigned filter also reduces the training complexity of the model. The experimental results show that the performance of the RVTDCNN model is almost the same as the NN models and the multilayer NN models. Meanwhile, compared with the abovementioned models, the coefficient number and computational complexity of the RVTDCNN model are significantly reduced. This advantage is noticeable when the memory effects of the PA are increased by using wider signal bandwidths.

Localization techniques are becoming key to add location context to the Internet-of-Things (IoT) data without human perception and intervention. Meanwhile, the newly emerged low-power wide-area network (LPWAN) and 5G technologies have become strong candidates for mass-market localization applications. However, various error sources have limited localization performance by using such IoT signals. This article reviews the IoT localization system through the following sequence: IoT localization system review, localization data sources, localization algorithms, localization error sources and mitigation, and localization performance evaluation. Compared to the related surveys, this article has a more comprehensive and state-of-the-art review on IoT localization methods, an original review on IoT localization error sources and mitigation, an original review on IoT localization performance evaluation, and a more comprehensive review of IoT localization applications, opportunities, and challenges. Thus, this survey provides comprehensive guidance for peers who are interested in enabling localization ability in the existing IoT systems, using IoT systems for localization, or integrating IoT signals with the existing localization sensors.

In this paper, a novel multi-stream spatial digital predistortion (DPD) technique is proposed to model and linearize the fully-connected (FC) hybrid beamforming (HBF) transmitters. The proposed scheme solves the DPD implementation issue in the FC HBF array by estimating and linearizing the beam signals instead of the individual PAs. In FC HBF systems, significant intermodulation (IMD) between different transmit signals will be generated due to the analog beamforming and combining network upstream of the power amplifiers (PAs). The IMD beams will end up being radiated in different directions and some of them might fall in the linear beam directions. Therefore, multi-input DPD blocks using a practical multi-variable model are constructed for each RF chain to eliminate the complicated inner- and cross-channel IMDs of the beam signals. Simulations on a 4-stream 64-element FC HBF array and experimental tests on a 2-stream 4-element system are carried out to benchmark the proposed DPD technique against the conventional techniques. Better than 13 dB adjacent channel power ratio (ACPR) improvement and 12 dB normalized mean square error (NMSE) improvement have been achieved by the proposed DPD technique.

Massive multi‐input–multi‐output (MIMO) is expected to be an eminent technique to meet the demands of high system capacity and data rates of wireless networks in 5G wireless communication. However due to inherent imperfections of the transmitter such as power‐amplifier (PA) non‐linearity and crosstalk, practically, the signal quality suffers and does not reap sufficient benefits from the various MIMO techniques. Digital predistortion (DPD) is a popular technique for single‐input–single‐output transmission to enhance signal quality. This study examines the issue of high DPD's complexity in mitigating imperfections in MIMO transmitters. This work proposes a less complex, novel DPD model for linearising large‐scale MIMO transmitters along with its characterisation procedure. The proof‐of‐concept is provided with the measurement setup containing 4 1 MIMO transmitters in the presence of non‐linear crosstalk, linear crosstalk, and strong PA non‐linearity. The proposed model performs comparably to the state‐of‐art DPD models like parallel Hammerstein and dual‐input crosstalk mismatch with lower number of floating‐point operations (flops). The proposed model improves adjacent channel power ratio up to dBc and error vector magnitude up to 1.08% for LTE signal of 40 MHz bandwidth.

Highly efficient power amplifiers (PAs) and associated linearization techniques have been developed to accommodate the explosive growth in the data transmission rate and application of massive multiple input multiple output (mMIMO) systems. In this paper, energy-efficient integrated Doherty PA monolithic microwave integrated circuits (MMICs) and linearization techniques are reviewed for both the sub-6 GHz and millimeter-wave (mm-Wave) fifth-generation (5G) mMIMO systems; different semiconductor processes and architectures are compared and analyzed. Since the 5G protocols have not yet been finalized and PA specifications for mMIMO are still under consideration, it is worth investigating novel design methods to further improve their efficiency and linearity performance. Digital predistortion techniques need to evolve to be adapted in mMIMO systems, and some creative linearity enhancement techniques are needed to simultaneously improve the compensation accuracy and reduce the power consumption.

In this paper, a low-feedback-sampling-rate digital predistortion (DPD) method is proposed for wideband wireless transmitters and radio-frequency power amplifiers (PAs). This DPD method inserts a non-ideal real band-pass filter into the feedback loop to limit the feedback bandwidth. Meanwhile, to recover the band-limited feedback signal, it introduces a signal-recovery module that is based on the deep neural network (DNN). A data-preprocessing technique is proposed to reduce the amount of input data for the DNN and thereby significantly reducing its structural complexity. Also, the use of DNN makes it feasible to implement off-line training. Both the simplicity of the proposed DNN and the availability of off-line training reduce the system complexity in DPD. Experimental validation was performed on a PA driven by wideband orthogonal-frequency-division-multiplexing (OFDM) signals. The results demonstrated the superiority of the proposed method in under-sampling applications. The proposed DPD method achieved the same linearization performance as the state-of-art DPD methods while requiring a sampling rate that was approximately 5% less. Meanwhile, the proposed DPD method has been validated to have stronger anti-noise and generalization capabilities.

A digital predistorter, modeled by an augmented real-valued time-delay neural network (ARVTDNN), has been proposed and found suitable to mitigate the nonlinear distortions of the power amplifier (PA) along with modulator imperfections for a wideband direct-conversion transmitter. The input signal of the proposed ARVTDNN consists of Cartesian in-phase and quadrature phase ( I/Q ) components, as well as envelope-dependent terms. Theoretical analysis shows that the proposed model is able to produce a richer basis function containing both the desired odd- and even-order terms, resulting in improved modeling capability and distortion mitigation. Its actual performance has been validated through extensive simulations and experiments. The results show that the compensation and hardware impairment mitigation capabilities of the ARVTDNN are superior to the existing state-of-the-art real-valued focused time-delay neural network (RVFTDNN) by 3-4 dB for the adjacent channel power ratio and by 2-3 dB in terms of the normalized mean square error. Other important features of the proposed model are its reduced complexity, in terms of the number of parameters and floating-point operations, and its improved numerical stability compared to the RVFTDNN model.

Multi‐band transmitter systems are evolving to support the smooth transition from 4G to 5G communication systems. Moreover, recent developments of multi‐band and ultra‐wideband power amplifiers have led to a possible scenario where the second carrier signal is transmitted at the harmonic frequency of the first carrier signal. This results in harmonic interference from the first carrier signal as well as additional cross‐modulation and intermodulation distortion (IMD) components, which cannot be filtered out. The computational and memory requirements for digital predistortion (DPD) in such scenario increase drastically to include all interference terms. This study presents a novel two‐dimensional curtailed harmonic memory polynomial (2D‐CHMP) model to capture harmonic interferences, cross‐modulation and IMDs. The model complexity and memory requirement of 2D‐CHMP are very less as compared to the state‐of‐the‐art two‐dimensional harmonic memory polynomial (2D‐HMP) model. For proof‐of‐concept, it is shown with two different measurement setups that the proposed 2D‐CHMP DPD provides similar linearisation performances as compared to the 2D‐HMP DPD with less number of coefficients and computational complexity. As a study, it is shown that the proposed model can be further adapted to a low‐precision (low‐bit) environment by utilising principal component analysis.

In this paper, a novel synthesis technique for dual-frequency rectifier for ambient RF energy harvesting is proposed. For the first time, a fully distributed version of dual-frequency resistance compression network (RCN) is introduced. The proposed RCN utilizes the dual- frequency characteristic of the c-type coupled lines terminated into real impedance. The design technique is fully analytical based on closed-form design equations. Extensive simulations have been carried out to illustrate the proposed idea. The obtained results outperform the earlier reported lumped element network and provides a minimum 10% improvement in the RF-to-DC conversion efficiency at -20 dBm input power. The proposed technique can potentially serve as a starting point for the dual-frequency RF rectifier design.

An augmented Hammerstein model (AHM) is proposed for the first time to calibrate a six‐port‐based receiver (SPR) and to recover the in‐phase I and the quadrature Q components of a modulated wideband RF signal. The proposed model is intended to provide a good compromise between complexity and accuracy. To verify the performance of the resulting calibration approach, an experimental validation has been performed with an SPR driven by wideband modulated signals with different bandwidths. An error vector magnitude between the transmitted and received signals of 2.17 and 1.33% has been reported for 64‐QAM signals with 4 and 2 MHz bandwidths, respectively. The obtained measurement results have revealed the robustness and the superiority of the AHM‐based single‐step calibration technique compared with the two‐step conventional procedure. Moreover, the AHM achieved the same performance as the published memory polynomial model while requiring ∼60% less coefficients leading to a less complexity calibration procedure with a lower number of calibration parameters and flops.

In this study, a novel model for the joint compensation of dual‐band power amplifier (PA) distortion and in‐phase/quadrature (I/Q) imbalance, which are the dominant impairments of wireless signal transmitters, in a complexity reduced structure is proposed. This model is mainly based on the augmented Hammerstein approach in a Cartesian form so that a static block is intended to model the PA non‐linearity and the modulator I/Q imbalance while a finite impulse response filter based block is used to model the PA memory effects. The proposed approach reduces significantly the complexity of the proposed model compared with the recently published memory polynomial models. Experiments with and without I/Q modulator impairments have been carried out on a dual‐band PA to verify the accuracy and the performance of the linearisation technique based on the proposed model. The experimental results have revealed a good impairments reduction with much less model coefficients compared with the recently published ones.

Deploying a power saving mode (PSM) is considered an effective solution for saving energy; however, a key challenge is how to simultaneously save energy and support a required level of quality of experience (QoE) using PSM for voice over IP (VoIP) services. This paper aims at developing a novel Markovian-based evaluation framework that assesses the energy consumption and QoE, achieved by a fixed sleeping time-based PSM. Based on this framework, a novel QoE-aware PSM is developed, which exploits the ON-OFF characteristics of a VoIP session to further improve the energy saving, while accounting for the effect of bursty losses on the QoE. The QoE and energy consumption achieved by the proposed PSM are evaluated via solving a system of linear equations. This facilitates the analytical formulation of the QoE/energy tradeoff that is needed for the successful integration of this QoE-aware PSM within the traffic offloading mechanisms. Numerical results validate the accuracy of the performance evaluation framework and verify the efficacy of the proposed QoE-aware PSM in saving energy while assuring a desired level of QoE. The Pareto-optimal operational regime show that the proposed QoE-aware PSM significantly reduces power consumption at a desired level of QoE compared with its counterparts.

This study presents an adaptive predistortion algorithm based on direct learning approach to compensate for the non‐linearities of a power amplifier (PA) exhibiting memory effects. The proposed algorithm implements the steepest descent technique on an odd‐order memory polynomial model to optimise the predistorter coefficients. The performance of the proposed algorithm is validated using a harmonically tuned broadband PA driven by long‐term evolution 20 MHz signal. Measurement results confirmed the robustness of the proposed technique by adapting the coefficients of the predistorter to the changes in average input power, drain bias, and gate bias of the PA. The linearisation using the proposed algorithm is compared to the traditional uncompensated case and results are presented. For changes in average input power, gate bias and drain bias levels, the normalised mean square error shows substantial enhancement when the predistortion coefficients are updated using the proposed algorithm.

In this paper, an augmented crossover memory polynomial model (A-COMPM) is proposed and developed which can be used for characterizing and linearizing multiple-input multiple-output (MIMO) transmitters in the presence of linear and nonlinear crosstalk. The proposed model significantly improves the performance of the crossover memory polynomial model (CO-MPM) by more accurately incorporating the effect of crosstalk. The proposed model performs comparably to the 2 x 2 parallel Hammerstein (2 x 2 PH) model, while requiring the same number of coefficients as CO-MPM and a lower number of coefficients than the 2 x 2 PH. The model was tested for forward modeling and digital predistortion (DPD) applications in the presence of both linear and nonlinear crosstalk. Experimental results show that the model outperforms the CO-MPM and 2 x 2 PH DPDs, at a lower number of coefficients compared to both models. Furthermore, the issue of numerical stability of the DPD

This paper develops a stochastic geometry-based analytical approach for calculating the throughput reliability of a cloud-radio access network (C-RAN) comprising randomly distributed remote radio heads (RRHs) and randomly located users. A tunable distance-based RRH transmit power control mechanism along with cooperative joint transmissions by the RRHs is employed to achieve power savings and high throughput reliability. The analytical result for the throughput reliability serves as input to analysis of per user achievable average rate and C-RAN network-level performance metrics of spectral efficiency and energy efficiency. The analytical results are validated by Monte Carlo simulation results with good agreement, thus confirming the accuracy of the developed analytical approach. The key finding from the analysis is that by carefully tuning the RRH transmit power and cooperation parameter (cluster radius), it is possible to realize a threefold improvement in the energy efficiency along with 108% enhancement in the spectral efficiency of C-RANs. Copyright © 2016 John Wiley & Sons, Ltd.

This paper proposes a new peak-to-average power ratio (PAPR) reduction technique using a polynomial soft clipping function identified through a nonlinear constrained optimization. The power efficiency optimization problem of a linearized power amplifier can be considered as the minimization of the PAPR constrained by meeting the spectral mask requirements of the signal standard. It is demonstrated that the proposed approach can reduce the PAPR from 9.9 to 5.5 dB while meeting the spectral mask of the wideband code-division multiple-access standard. To compare the results with the traditional clipping and filtering method, the 5.5-dB PAPR clipped signal using the clipping and filtering technique was compared with the soft clipped signal. With the same efficiency, the error vector magnitude (EVM) for the soft clipped signal improved from 4.5% to 1.3% using post-compensation. Later, clipping and filtering are combined with the soft clipping technique. It is shown that the combined structure can reduce the PAPR to 3.4 dB while passing the adjacent channel power ratio and EVM requirements. The performance of the proposed method in the presence of additive white Gaussian noise and fading channels has been evaluated for 64QAM modulations using orthogonal frequency-division multiplexing modulated symbols.

Narrow band interference NBI deteriorates the quality of the spectrum, leading to a poorer performance of modern universal mobile telecommunication system UMTS spread spectrum systems. The linear prediction algorithm is one of the most significant techniques to overcome NBI and enhance the performance of UMTS systems. In this paper, a modified linear prediction algorithm is proposed for NBI suppression in a conditionally stationary environment. This modification improves the error energy estimation in the auto-regression model of the linear prediction. The convergence of the proposed algorithm is evaluated, and its robustness is verified using Kullback-Leibler metrics for conditionally stationary NBI signals. Computer simulations are carried out, and the obtained results demonstrate the performance of the proposed algorithm and its compliance with UMTS protocols. Copyright © 2012 John Wiley & Sons, Ltd.

Spurious intermodulation components have recently been identified as a major problem in carrier aggregation mobile transmitters with multi-band power amplifiers (PAs). This article presents novel adaptive digital predistortion (DPD) solutions with reduced complexity in both the predistortion processing and the feedback paths, to tackle this problem. Compared with conventional DPDs which aim to linearize the whole transmit bandwidth, the proposed technique aims at mitigating only those intermodulation components which are most problematic from the spurious emission limit perspective. The proposed technique is verified with extensive simulations in various 3GPP LTE-A carrier aggregation scenarios, showing that the intermodulation spurs can be efficiently mitigated below the spurious emission limit with relatively small back-offs.

This study addresses the ill‐conditioning problem of the memory polynomial (MP) model with application to the predistortion of highly non‐linear power amplifiers with memory effects. A resource‐efficient lattice‐based MP structure built using the cascade of a MP generator and a lattice predictor is proposed to overcome the ill‐conditioning of the MP's data matrix. The proposed model performances are benchmarked against those of the MP model as well as the orthogonal MP model. The experimental results demonstrate the suitability of the proposed predistorter as it achieves similar performance in the time and the frequency domains compared to the MP counterpart while alleviating its ill‐conditioning problem.

A novel generalised twin‐box model is proposed for the mutual compensation of modulator imperfections and power amplifier (PA) distortion. It is composed of two cascaded boxes, a dual branch of simplified Volterra filters for the joint characterisation of the mild non‐linear dynamic memory effects of the PA and modulator imperfections. The second box is a look‐up table for characterising the highly non‐linear static distortion exhibited by the PA. Hence, the proposed model has reduced complexity in comparison with the state‐of‐the‐art models, owing to the separate identification of the dynamic and static effects of the PA. The model validation is carried out using a Class AB PA, and the proposed model showed significant improvement in performance as well as reducing the computational complexity of the model.

The oversampling requirement in a delta-sigma modulator (DSM) is considered one of the limiting factors toward its employment in current high-frequency applications, such as wireless software defined radio (SDR) systems. This paper advances that the critical requirement for DSMs is high-frequency processing and not a high-oversampling ratio. A single-bit semiparallel processing structure to accomplish the high-frequency processing is proposed in this paper. Using the suggested low-oversampling digital DSM architecture, high-speed, high-complexity computations, which are normally required for wireless applications, are executed simultaneously. This facilitates the design of embedded SDR multistandard transmitters using commercially available digital processors. The most favorable application of the proposed single-bit DSM is to build an radio frequency transmitter that includes a one-bit quantifier with two-level switching power amplifier for both high linearity and high efficiency. Performance analysis is carried out by using MATLAB simulations, which shows a reduction of the oversampling ratio by a factor of 16 (for a baseline oversampling ratio of 256) with the same signal-to-noise ratio (SNR). The proposed DSM is also implemented on a field-programmable gate array (FPGA) board and its performance is validated by using a code division multiple access signal. The bandwidth of the output signal is increased four times without increasing the processing frequency. Simultaneously, quality of the output signal remains the same but FPGA resource usage is increased by a factor of three.

This paper demonstrates a new channel-selective multi-cell processing predistortion technique that compensates for the nonlinearities of multi-carrier transmitters. The proposed technique uses independent processing cells to compensate for the intra-band and inter-band distortions of nonlinear transmitters. This frequency-selective feature of the proposed technique significantly reduces the minimum sampling rate requirements of analog-to-digital and digital-to-analog converters, which are a critical issue for conventional digital predistortion (DPD) techniques dealing with wideband signals. The proposed technique was evaluated with four-carrier (1001) and six-carrier (100001) WCDMA signals, using a nonlinear 10-Watt power amplifier. The performance of the proposed technique was compared with look-up table, multi-branch and recently proposed frequency-selective DPDs, in terms of adjacent-channel power ratios (ACPRs) and sampling rate requirements. The proposed technique improved the ACPR and the carrier-to-intermodulation power ratio (CIMPR) of the 1001 WCDMA signal by more than 13 dB and 10 dB, respectively.

This study proposes a new technique for the extraction of static non-linearities in wideband transmitters by launching a simple sinusoidal wave within the bandwidth of the system. The transmitter is first characterised under a two-carrier wideband code division multiple access (WCDMA) drive signal and modelled using a memory polynomial model. Two types of memoryless digital predistorters are then synthesised and applied to the amplifier model. The first predistorter is derived from the averaging of the measured data under the two-carrier WCDMA signal, while the second is derived using a sinusoidal wave signal excitation. Discrepancies between the two predistortion functions are illustrated, demonstrating that the predistorter using the averaging technique is biased by the presence of linear memory effects. The results show that the residual distortions at the output of the linearised power amplifier are different and more present when using the sine wave excitation technique compared with the averaging technique. This finding indicates that the sine wave-based technique is more rigorous for de-embedding the static non-linearity from the overall non-linear behaviour, which corroborates the validity of the proposed approach in extracting the true static behaviour of the system and its pertinence for the accurate extraction and quantification of memory effects.

A design technique to realise a low-complexity multiple-input multiple-output (MIMO) receiver using a time-multiplexed single front-end receiver is introduced. The architecture uses a simple front-end receiver where it delivers radio frequency signals to baseband section. The theory behind this architecture is analysed and the diversity gain of the proposed receiver is investigated. This simple MIMO receiver can provide the same diversity gain as the diversity gain of the multiple front-end. Moreover, the experimental studies are conducted to evaluate the diversity gain of the proposed architecture. Excellent agreement between the simulated and measurement results is obtained. The proposed architecture provides a new receiver design technique with lower complexity, power consumption and cost in MIMO systems.

This paper presents an overview of system-level solutions for green wireless communication infrastructure. It illustrates that a combination of high efficiency amplification system with a linearity restoration technique is unavoidable. Currently, Doherty power amplifiers along with digital predistortion technique are able to achieve high power efficiency. However, due to the limited bandwidth of digital predistortion systems (typically 20 MHz), feedforward based linearizers which result in significantly lower power efficiency are still considered for wideband solutions (up to 60 MHz). An experimental approach for extending the bandwidth of digital predistortion systems is reported. This setup is then applied for the linearization, using digital predistortion, of a Doherty power amplifier driven by an 8-carrier WCDMA signal having a total bandwidth of 40 MHz.

This paper presents a novel subsampling-based down-conversion topology for multistandard radio receiver design. This receiver topology is based on two subsampling stages. The first stage has a fixed RF subsampling frequency; however, the IF sampling frequency of the second stage is variable and depends on the standard being considered. This approach overcomes various undesirable effects related to the sampling frequencies and noise aliasing. By optimizing the choice of the RF subsampling clock frequency, complete multistandard RF bands are down-converted to the same IF band. Quadrature baseband channel downconversion is achieved by a tunable IF sampling frequencies clock. A tunable band-pass RF filter and an IF band-pass filter are designed to perform anti-aliasing and limit wideband noise. A generic design methodology is proposed and validated through its application to a GSM, UMTS and IEEE-802.11g multistandard receiver. Simulation results of this receiver design example confirm the validation of proposed subsampling receiver topology and show the efficiency of the design methodology.

A new RF modified linear amplifier using nonlinear components (LINC) architecture for wireless communication links is proposed and evaluated in this work. The layout of the new architecture is presented and the simulation results are presented to show the performance under different operation conditions and channel types. Results show that the overall power efficiency of this architecture is improved by more than 400% when compared with that of the regular LINC amplifier architecture.

In this paper a real-valued time-delayed neural network (RVTDNN) is utilized to build a baseband behavioral model of a 3G power amplifier. Based on the inphase and quadratic components of the input and output signals of a high power amplifier, a three-layer RVTDNN is firstly trained in Matlab and then implemented in Agilent design system software. In order to speed up the training process, a second-order learning algorithm namely scaled conjugate gradient method (SCGM) is employed to extract the RVTDNN model parameters (weights and biases). The comparison of the simulation based results to the measured ones reveals the strong ability of the identified RVTDNN to accurately predict the dynamic nonlinear behavior of a 90-Watt LDMOS power amplifier under a two-carrier 3GPP-FDD excitation signal.