This paper presents a hardware approach to the design of fuzzy controllers which, by exploiting some peculiar characteristics of fuzzy logic computation, allows one to save power consumption and increase computing speed. We show that the computation involved in a fuzzy controller has some statistic features that can be exploited by asynchronous computation. This paper presents a quantitative study of the statistical properties of fuzzy computation. A design methodology is introduced, and two experimental applications are shown.

A large fraction of software designs using microcontrollers is today adopting fuzzy logic algorithms and this fraction is likely to increase in the future. Hardware implementation of fuzzy logic ranges from standard microprocessors to dedicated ASICs and each different approach is targeted to a different application domain or market area. In this paper, we present an overview of the computational complexity of the fuzzy inference process and the various techniques adopted for fuzzy control tasks, highlighting the tradeoffs that can guide a system designer toward correct choices according to application features and cost/performance issues. In addition, we detail three case studies of architectures that address three different market segments in the fuzzy hardware scenario: dedicated fuzzy coprocessors, RISC processors with specialized fuzzy support and application specific fuzzy ASICs.>

VLIW processors are viewed as an attractive way of achieving instruction-level parallelism because of their ability to issue multiple operations per cycle with relatively simple control logic. They are also perceived as being of limited interest as products because of the problem of object code compatibility across processors having different hardware latencies and varying levels of parallelism. The author introduces the concept of delayed split-issue and the dynamic scheduling hardware which, together, solve the compatibility problem for VLIW processors and, in fact, make it possible for such processors to use all of the interlocking and scoreboarding techniques that are known for superscalar processors.>