Surface electromyography (sEMG) is a widely employed bio-signal that captures human muscle activity via electrodes placed on the skin. Several studies have proposed methods to remove sEMG contaminants, as non-invasive measurements render sEMG susceptible to various contaminants. However, these approaches often rely on heuristic-based optimization and are sensitive to the contaminant type. A more potent, robust, and generalized sEMG denoising approach should be developed for various healthcare and human-computer interaction applications. This paper proposes a novel neural network (NN)-based sEMG denoising method called TrustEMG-Net. It leverages the potent nonlinear mapping capability and data-driven nature of NNs. TrustEMG-Net adopts a denoising autoencoder structure by combining U-Net with a Transformer encoder using a representation-masking approach. The proposed approach is evaluated using the Ninapro sEMG database with five common contamination types and signal-to-noise ratio (SNR) conditions. Compared with existing sEMG denoising methods, TrustEMG-Net achieves exceptional performance across the five evaluation metrics, exhibiting a minimum improvement of 20%. Its superiority is consistent under various conditions, including SNRs ranging from -14 to 2 dB and five contaminant types. An ablation study further proves that the design of TrustEMG-Net contributes to its optimality, providing high-quality sEMG and serving as an effective, robust, and generalized denoising solution for sEMG applications.

Surface electromyography (sEMG) recordings can be influenced by electrocardiogram (ECG) signals when the muscle being monitored is close to the heart. Several existing methods use signal-processing-based approaches, such as high-pass filter and template subtraction, while some derive mapping functions to restore clean sEMG signals from noisy sEMG (sEMG with ECG interference). Recently, the score-based diffusion model, a renowned generative model, has been introduced to generate high-quality and accurate samples with noisy input data. In this study, we proposed a novel approach, termed SDEMG, as a score-based diffusion model for sEMG signal denoising. To evaluate the proposed SDEMG approach, we conduct experiments to reduce noise in sEMG signals, employing data from an openly accessible source, the Non-Invasive Adaptive Prosthetics database, along with ECG signals from the MIT-BIH Normal Sinus Rhythm Database. The experiment result indicates that SDEMG outperformed comparative methods and produced high-quality sEMG samples. The source code of SDEMG the framework is available at: https://github.com/tonyliu0910/SDEMG

This paper presents a power-efficient autonomous current adaptation input driver (ACAID) for analog-to-digital converters (ADCs), which employs floating-gate transistors to provide reconfigurability. The proposed ACAID autonomously increases the supply current at the onset of the tracking phase, achieving a high slew rate. As the driver output voltage gradually follows the input signal in the RC-settling or hold phase, the supply current successively diminishes back to the original low quiescent level. The required sensing and actuating circuits for current adaptation are inherent components in the adopted capacitive feedback topology. A prototype version of the proposed ACAID has been designed and fabricated in a$0.35\um$CMOS process, along with integrated charge programming circuits and a 10-bit successive approximation register ADC. With$0.5\pF$sampling capacitors loading the driver, the proposed ACAID achieves$-70.1\dB$total harmonic distortion (THD) with a$100\kHz$input signal with$2.8\Vpp$amplitude. When connected to an on-chip ADC with a$200\kHz$sampling rate, the measured effective number of bits (ENoB) near the Nyquist rate is 9.1. The proposed ACAID saves more power as the input frequency increases or when the portion of the tracking period reduces. The prototyped driver circuit can save$49.5\%$power consumption when the input frequency is$100\kHz$with a$10\%$duty cycle for tracking. The power-saving ratio can be up to$76.2\%$when the sampling rate increases to$1\MHz$.

Electrocardiogram (ECG) artifact contamination often occurs in surface electromyography (sEMG) applications when the measured muscles are in proximity to the heart. Previous studies have developed and proposed various methods, such as high-pass filtering, template subtraction and so forth. However, these methods remain limited by the requirement of reference signals and distortion of original sEMG. This study proposed a novel denoising method to eliminate ECG artifacts from the single-channel sEMG signals using fully convolutional networks (FCN). The proposed method adopts a denoise autoencoder structure and powerful nonlinear mapping capability of neural networks for sEMG denoising. We compared the proposed approach with conventional approaches, including high-pass filters and template subtraction, on open datasets called the Non-Invasive Adaptive Prosthetics database and MIT-BIH normal sinus rhythm database. The experimental results demonstrate that the FCN outperforms conventional methods in sEMG reconstruction quality under a wide range of signal-to-noise ratio inputs.

A cold start-up circuit for thermoelectric energy harvesting systems is presented in this paper. The proposed cold start-up circuit shares the energy harvesting inductor and load capacitor with the main boost converter, so no extra off-chip components are required, resulting in a small form factor. The start-up circuit comprises a stacked ring oscillator, a pair of low-voltage charge pumps, a low-power voltage detector, a reset switch, and two power switches. A prototyped chip for concept proving is designed and fabricated in a$0.18\ \mu \mathrm{m}$CMOS process. The measured waveforms demonstrate that the prototyped cold start-up chip can boost an input voltage of 300mV up to 1V within 950ms when the loading capacitance is$0.1\ \mu \mathrm{F}$.

In this paper, a four-channel floating-gate-based analog front-end (AFE) integrated circuit is presented. Each channel consists of a low noise amplifier (LNA), two operational-transconductance-amplifier-capacitor (OTA-C) biquadratic filters, and two buffer amplifiers. Floating-gate transistors deployed in a two-dimensional array are utilized to facilitate circuit reconfigurability and to achieve better power efficiency. Floatinggate programming circuities are also designed on-chip. Furthermore, a serial-peripheral interface (SPI) circuit with floating-gate transistors as non-volatile memories is adopted as the circuit parameter storage as well as the control interface during floatinggate programming. A prototype chip is designed and fabricated in a 0.35 μm CMOS process, occupying an area of 13.62 mm2. The measured current consumption of a single sensing front-end channel is only 76 nA with the noise efficiency factor of 5.82. The measured output signal magnitude is 564.3 mVppwith 1% total harmonic distortion.

In this paper, a resonator-based non-invasive material sensor and its sensor interface circuits are presented. The sensing interface circuits detect the resonant frequency and resonator loss caused by the material under test. The readouts of resonance frequency and resonator loss correspond to the real and the imaginary parts of the sample relative permittivity respectively. The resonant amplitude is maintained constant by injecting different amounts of tail current to the resonator from a current mode digital-to-analog converter (I-DAC). The control bits of this I-DAC indicates the loss of the resonator. The interface circuit employs an integration-and-count approach to digitize the resonance frequency directly. The signal-to-noise ratio increases with the integration interval without being limited by the resolution of a dedicatedly designed analog-to-digital converter. A prototyped chip has been designed and fabricated in a 0.18 μm CMOS process. The preliminary measurement results show that the proposed sensor system can distinguish air, deionized water, and different concentrations of ethanol and methanol.

A linearity efficiency factor (LEF) is proposed in this paper to quantify the trade-off among linearity, bandwidth, and power consumption in designing differential pair or operational transconductance amplifier (OTA) circuits. The unitless LEF can be used to evaluate the trade-off efficiency of a circuit topology without considering the effects of input attenuation nor the bias current level when all transistors are biased in the subthreshold region. According to this proposed figure of merit, a power-efficient linearized differential pair and a fully differential OTA are proposed and evaluated. The OTA, which is composed of a complementary pair of the linearized differential pairs and a floating-gate common-mode feedback scheme, exhibits 7.8 times better power efficiency than a basic OTA with capacitive input attenuation while achieving the same transconductance and linearity performance.

The Reconfigurable Smart Sensory Chip (RSSC) is a powerful tool for fast prototyping sensory microsystems. Innovative design ideas can be quickly realized and tested in hardware without doing time-consuming and expensive silicon fabrication. The RSSC is a large-scale floating-gate based IC containing 8 universal sensor interface blocks, each of which can be configured for voltage sensing, capacitive sensing, or current sensing, and 28 configurable analog blocks. The outputs of the interface circuits can be multiplexed out in a time-division sequence or can be routed to the configurable analog blocks for further analog signal processing or data conversion. With more than 50,000 programmable elements and on-chip programming circuitry, RSSC is an extremely powerful tool to develop and test a great variety of smart sensory microsystems in minutes.

A 16 × 16 programmable analog radial-basis-function (RBF) based classifier is demonstrated. The distribution of each feature is modeled by a Gaussian function, which is realized by a proposed floating-gate bump circuit having bell-shaped transfer characteristics. The maximum likelihood, mean, and variance of the distribution are stored in floating-gate transistors and are independently programmable. By cascading these floating-gate bump circuits, the overall transfer characteristics approximate a multivariate Gaussian distribution with a diagonal covariance matrix. An array of these circuits constitutes a compact RBF-based classifier. When followed by a winner-take-all circuit, the analog classifier can implement vector quantization. Automatic gender identification is implemented on a 16 × 16 analog vector quantizer chip as one possible audio application of this work. The performance of the analog classifier is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task.

We propose an analog VLSI approach to implementing the projection neural networks adapted for the support vector machine with radial-basis kernel functions, which are realized by a proposed floating-gate bump circuit with the adjustable width. Other proposed circuits include simple current mirrors and log-domain filters. Neither resistors nor amplifiers are employed. Therefore it is suitable for large-scale neural network implementations. We show the measurement results of the bump circuit and verify the resulting analog signal processing system on the transistor level by using a SPICE simulator. The same approach can also be applied to the support vector regression. With these analog signal processing techniques, a low-power adaptive analog system without any analog-to-digital convertor but with the capability of learning, classifying, and regressing becomes feasible.

A compact analog programmable multi-dimensional radial basis function (RBF) based classifier is demonstrated. The probability distribution of each feature in the templates modeled by a Gaussian function is approximately realized by the transfer characteristics of a floating-gate bump circuit. The maximum likelihood, the mean, and the variance can be inde- pendently programmed. By cascading these floating-gate bump circuits, the transfer characteristics approximate a multivariate Gaussian function with a diagonal covariance matrix. An array of these circuits constitute a compact multi-dimensional RBF- based classifier. When followed by a winner-take-all circuit, the RBF-based classifier forms an analog vector quantizer. We use receiver operating characteristic curves and equal error rate to evaluate the performance of our analog classifiers. We show that the analog classifier performance is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task.

This paper describes a high signal-to-noise ratio capacitive sensing transducer with high power efficiency and high area efficiency. The circuit is an example of capacitive circuit and is based on a capacitive feedback charge amplifier. 78.6dB SNR in audio band is achieved with less than 0.5 /spl mu/W power consumption by making use of a floating-gate transistor. This design gives us the flexibility of controlling the charge on the floating node. The microphone sensor is interfaced with the amplifier to measure the performance of the transducer.