Thermal issues of 3D-ICs have become increasingly severe in recent years. Thus, thermal simulation is needed to ensure thermal safety during the design stage. However, performing thermal simulation iteratively requires a significant amount of time. As a result, a fast and accurate method for thermal prediction is a promising alternative to improve the turnaround time. In this paper, we propose a fast thermal prediction method using machine learning models. In the training phase, we employ two models: one for the initial three time steps and another for the subsequent time steps. To enhance prediction accuracy, we introduce two types of features: spaced-windowed features and time-decayed features. These features help us to capture spatial and temporal information effectively. In our experiment, the mean absolute error for the predicted temperature is 1.12°C, and the maximum error is 7.27 °C. In the prediction phase, we achieve a 116X speed-up compared to a commercial tool. With our proposed method, users can predict transient thermal profiles quickly and accurately to ensure thermal safety.

This paper presents an integrated IR-Informed Timing and Timing-Aware IR Optimization flow with an IR-drop predictor. The proposed flow couples an IR-Informed Timing Optimizer with a Timing-Aware IR Optimizer to consider the mutual impact between IR-drop and timing during optimization. Then, we leverage a fast ML-based IR-drop predictor to quickly estimate the IR-drop after each iteration of optimization, which enables fast switching between the IR optimizer and timing optimizer. We further propose Feature Approximation to speed up the inference time of the IR-drop predictor. On two 7nm designs, the proposed flow closes timing and eliminates at least 90.6% of IR-drop violations. The Feature Approximation achieves 67% speed up in the runtime of the overall flow. Our optimization flow can be applied to a 945k-cell design with 7,578 IR-drop violations within 3 hours, demonstrating its practicality.

Thermal issues during testing of Very Large Scale Integration (VLSI) chips have become more severe as design complexity increases. Test frequency optimization is needed because high test frequencies can cause thermal damage to circuits under test (CUT), while low test frequencies can result in long test time. In this paper, we propose three techniques to minimize the test time of ATPG scan tests without peak temperature violation. First, we propose a single test frequency optimization using machine learning predicted power maps. Second, we partition a test schedule into subschedules and perform multiple test frequency optimization for each subschedule to further reduce test time. Third, we show that we can partition a test schedule by our proposed Power Gap to obtain an even shorter test time. Our experimental results show that the total test time at our optimized multiple test frequencies is 45.91% shorter than the total test time at the original single test frequency.

Existing approaches to timing analysis under uncertainty are based on restrictive assumptions. Statistical STA techniques assume that the full probabilistic distribution of parameter uncertainty is available; in reality, the complete probabilistic description often cannot be obtained. In this paper, a new paradigm for parameter uncertainty description is proposed as a way to consistently and rigorously handle partially available descriptions of parameter uncertainty. The paradigm is based on a theory of interval probabilistic models that permit handling uncertainty that is described in a distribution-free mode- just via the range, the mean, and the variance. This permits effectively handling multiple real-life challenges, including imprecise and limited information about the distributions of process parameters, parameters coming from different populations, and the sources of uncertainty that are too difficult to handle via full probabilistic measures (e.g. on-chip supply voltage variation). Specifically, analytical techniques for bounding the distributions of probabilistic interval variables are proposed. Besides, a provably correct strategy for fast Monte Carlo simulation based on probabilistic interval variables is introduced. A path-based timing algorithm implementing the novel modeling paradigm, as well as handling the traditional variability descriptions, has been developed. The results indicate the proposed algorithm can improve the upper bound of the 90 th-percentile circuit delay, on average, by 5.3 % across the ISCAS’85 benchmark circuits, compared to the worst-case timing estimates that use only the interval information of the partially specified parameters.

Reliable prediction of parametric yield for a specific design is difficult; a significant reason is the reliance of the yield estimation methods on the hard-to-measure distributional properties of the process data. Existing methods are inadequate when dealing with real-life distributions of process and environmental parameters, and limited availability of parameter data during early design. This paper proposes a robust technique for full-chip parametric yield estimation; the proposed work is based on the rigorous notions of non-parametric robust statistics which permits estimation based on the knowledge of the range and the limited number of moments (e.g. mean and variance) of the parameter distributions. Fully or partially specified process and environmental parameters can be described by robust representations, and used to estimate probabilistic bounds for leakage dissipation. The proposed approach is applied to estimating the chip-level parametric yield. The experimental results show that the robust estimation algorithm improves the total leakage estimate by 5-13% at the 99th percentile across distinct frequency bins, compared to using only the intervals of partially-specified parameters.

An efficient path-based statistical timing analysis algorithm that can handle arbitrary causes of delay correlations is proposed in this paper. The algorithm derives bounds for the cumulative distribution function (cdf) of the circuit delay using a new mathematical formulation based on the theory of stochastic majorization. Structural and interchip correlations between path delays can be taken into account. Because the analytical computation of an exact cdf for a probabilistic timing graph is infeasible, tight upper and lower bounds on the true cumulative distribution are derived. The efficiency and accuracy of the algorithm is demonstrated on a set of ISCAS'85 benchmarks. Across the benchmarks, the error of the 95th-percentile delay is 1.1%-3.3%, and the root-mean-square error of the cumulative probability is 1.7%-4.5%. The run time of the proposed algorithm for the largest benchmark circuit takes less than 4 s

Low-power circuits are especially sensitive to the increasing levels of process variability and uncertainty. In this paper we study the problem of leakage power minimization through dual Vth design techniques in the presence of significant Vth variation. For the first time we consider the optimal selection of Vth under a statistical model of threshold variation. Probabilistic analytical models are introduced to account for the impact of Vth uncertainty on leakage power and timing slack. Using this model, we show that the non-probabilistic analysis significantly (by 3x) underestimates the leakage power. We also show that in the presence of variability the optimal value of the second Vth must be about 30mV higher compared to the variation-free scenario. In addition, this model provides a way to compute the optimal value of the second Vth for a variety of process conditions.