With Moore's law progressively running out of steam, heterogeneous computing architectures have been powering the top supercomputers in the world for many years and are now finding broader adoption across the industry. The trend towards sustainable computing also requires domain-specific heterogeneous hardware architectures, which promise further gains in energy efficiency. At the same time, today's high performance computing applications have evolved from monolithic simulations in a single domain to multidisciplinary complex workflows. In this paper, we explore how these trends affect system design decisions and what this means for future computing system architectures.

The Cell Broadband Engine™ is a high performance supercomputer on a chip. It is a 64-bit Power Processor compatible to Power Architecture applications and OS. This heterogeneous multi-core architecture sets a new performance standard for games and multimedia applications. It exploits parallelism while achieving high frequency. With a multi-core design, we are facing several obstacles from architecture, technology to physical design. This presentation will give an overview of the Cell architecture and the challenges we faced. We will also discuss how we addressed these challenges and successfully implemented the Cell Processor.

This paper reviews the design challenges that current and future processors must face, with stringent power limits and high frequency targets, and the design methods required to overcome the above challenges and address the continuing Giga-scale system integration trend. This paper then describes the details behind the design methodology that was used to successfully implement a first-generation CELL processor - a multi-core SoC. Key features of this methodology are broad optimization with fast rule-based analysis engines using macro-level abstraction for constraints propagation up/down the design hierarchy, coupled with accurate transistor level simulation for detailed analysis. The methodology fostered the modular design concept that is inherent to the CELL architecture, enabling a high frequency design by maximizing custom circuit content through re-use, and balanced power, frequency, and die size targets through global convergence capabilities. The design has roughly 241 million transistors implemented in 90 nm SOI technology with 8 levels of copper interconnects and one local interconnect layer. The chip has been tested at various temperatures, voltages, and frequencies. Correct operation has been observed in the lab on first pass silicon at frequencies well over 4GHz.

This talk will present the Cell processor, jointly developed by the STI (Sony-Toshiba-IBM) partnership. Cell is a non-homogeneous chip multiprocessor intended for general-purpose applications but with a particular emphasis on multimedia performance. The Cell processor combines a 64bit Power Architecture(TM) core with 8 Synergistic Processors. In many cases, it delivers more than an order of magnitude more performance than conventional PC processors. Cell achieves this performance and power efficiency improvement by a new division of labor between the Power core and the Synergistic Processors. Cell allows for a wide variety of programming models, a selection of which will be presented in this talk. We will end the talk by discussing some applications that seem to fit the Cell processor particularly well, and by indicating areas of further exploration.

A highly concurrent second-generation RISC (reduced-instruction-set computer) that combines a powerful RISC architecture with sophisticated hardware design techniques to achieve a short cycle time and a low cycles-per-instruction (CPI) ratio is described. Like earlier RISC processors, this design uses a register-oriented instruction set, the CPU is hardwired rather than microcoded, and it features a pipelined implementation. Unlike earlier RISC processors, however, several advanced architectural and implementation features are used, including separate instruction and data caches, zero-cycle branches, multiple-instruction dispatch, and simultaneous execution of fixed- and floating-point instructions. The CPU has a four-word data bus to main memory, a four-word instruction-fetch bus from the I-cache arrays, and a two-word data bus between the D-cache and floating-point unit. The CPU has a full 64-b floating-point engine, and thirty-two 64-b floating point registers in addition to thirty-two 32-b fixed-point registers. In a single cycle, four instructions can be executed simultaneously.>