In safety-critical applications such as biomedical and automotive electronics, soft errors induced by radiation particles pose a significant reliability concern. This paper presents a novel Filtering Buffer-based D Flip-Flop (FB-DFF) designed to enhance radiation hardening while minimizing area and timing overheads. The FB-DFF integrates a Filtering Buffer (FB) and an Auto Delay Element (ADE) to effectively filter out transient errors and ensure the correct input signal is latched. The Single-Master Dual-Slaves (SMDS) architecture further prevents error propagation to the output. Experimental results demonstrate that FB-DFF can resist radiation particles below 77 LET, providing full protection against both Single Event Transient (SET) and Single Event Upset (SEU). Compared to existing designs, FB-DFF reduces area overhead by 44% and timing overhead by 144% at the chip level, making it a highly efficient solution for radiation-hardened applications. The proposed FB-DFF offers a balanced trade-off between radiation hardening capability, area, and timing performance, making it suitable for integration into various safety-critical systems.

Single-Event Double-Node Upsets (SEDUs) increasingly compromise the integrity of storage cells like latches or flip-flops, especially as technology scales down to sub-65nm nodes. Traditional RHBD (Radiation-Hardened by Design) strategies, such as DICE and TMR, crafted to counter Single-Event Node Upset (SEU), are proving to be inadequate to SEDU. Consequently, recent research suggests the use of expanded areas to shield circuits from SEDUs, yet this often results in disproportional overhead. In response, the LESER methodology emerged as an effective measure, introducing minimal redundancy while still guaranteeing full SEDU resilience. However, having mitigated SEDUs across different latches within ASAP7 (a predictive process), LESER calls for further improvement in three pivotal issues: (1) spacing impact, (2) dummy gates, and (3) device configuration. Thus, LESER-2 has been developed, targeting these three challenges in latches designed with two industrial process nodes. LESER-2 presents a dual-level architecture, encompassing both device and circuit strata. At the device level, LESER-2 replaces the virtual process model card with industrial ones, significantly enhancing simulation accuracy concerning heavy ion impacts on transistors. Additionally, circuit-level layout modification within LESER-2 are meticulously calibrated to mitigate SEDUs in vulnerable node pairs. Empirical tests validate the LESER-2 modifications applied to latches under two industrial process nodes, accomplishing a 100% rate of soft error prevention while incurring an average area overhead of 16.5%, effectively resolving the three aforementioned issues.

Many existing soft-error-tolerant flip-flop designs (e.g., MDAD-FF, SETU-TOFF, SEDR-FF) apply delayed latching to mitigate strikes of radiation particles. However, according to AEC-Q100 (Grade 1), automotive electronics are permitted to operate at temperatures between −40°C to 125°C, resulting in two reliability issues: (1) protection failure and (2) timing degradation. At −40°C, these rad-hard FF designs are capable of providing a worst-case delay of only 113 ps, ineffective in protecting against 77-LET particles (which require 200 ps in 45 nm process). At 125°C, however, the performance of these FF designs may degrade to 386 ps, resulting in more timing violations. Therefore, RAV-FF is proposed to address these two issues by incorporating a MOSFET capacitance (MCAP) to generate sufficient delay to delay clock and a current-control transistor (CC) to stabilize delay at different temperature corners. Experimental results indicate that RAV-FF provides effective soft-error protection in the temperature range of −40°C to 125°C by ensuring a delay of at least 200 ps with only 3% variation.

Single-event-induced soft errors are serious issues in advanced nano-scale technology, causing malfunctions in systems. As the size of technology node decreases to sub-65nm with closer transistor spacing, single-event double-node upsets (SEDU) occur more frequently than single-event upsets (SEU). Previous studies handled SEDU by incorporating protection mechanisms in cell designs or modifying the physical layout. However, they have massive area overhead and SEDU cannot be fully prevented. In this paper, we propose a LESER framework to reconstruct the latch design, achieving 100% SEDU tolerance. Based on the concept of engineering change order (ECO), LESER contains a two-level analysis process to prevent SEDU with minimum modification on layout, including 1) device level and 2) circuit level. The device level extracts the current source model by TCAD simulation and the circuit level reconstructs the layout with scanning process, double-node injection test, and layout modification approach. Experiments show that the reconstructed design can achieve a 100% soft error protection rate with the costs of an increment of 6.4% in area, 1% in timing and power penalty. The results indicate that LESER can fully prevent SEDU by reconstructing the latch with minimum performance penalties.

This paper study the payload data communication of multi-UAVs system, and propose the system architecture. Considering the asynchronous interference of multi-UAVs communication, the filtered-OFDM is introduced to suppress the out-of-band emission and mitigate the inter-subband interference. According to simulation results, the proposed multi-UAVs system based on F-OFDM that is superior to OFDMA scheme in asynchronous interference suppression and spectral efficiency. Finally, we valid the multi-UAVs communication system work well under the considered air-to-ground channel.

Epilepsy is a common neural disorder disease; about 0.5% of the global population has epilepsy [1]. Most patients take antiepileptic drugs to reduce their seizures. Among them, nearly one-third of the patients are drug-resistant epilepsy. The alternative treatment is the resection surgery of removing the epileptogenic zone. However, all above patients will still suffer seizures occasionally, which will influence the patients' quality-of-life, and further introduce danger and inconvenience to patients and people around. This paper presents the design and development of the smart headband for epileptic seizure detection. The headband consists of a fabric headband with flexible print circuit (FPC) inside and fabric electrodes on it. The whole system includes the following circuits: an analog front-end circuitry, an epileptic seizure detection tag (ESDT), and a Bluetooth Low Power (BLE) chip. The result of designed circuits yields a compact and low-power design of smart headband for epileptic seizure detection which is suitable for wearable usage. The epileptic seizure detection algorithm is validated by Children's Hospital Boston-MIT (CHB-MIT) EEG database [2].

For reducing soft error rate (SER) in system-level failures, this paper proposes a radiation-hardened design by Delay-Adjustable D Flip-Flop (DAD-FF), which can be generally applied to sequential circuits such as shift registers. DAD-FF, modified from the Built-In Soft-Error Resilience (BISER) latch, can be easily integrated in the CAD flow and its delay can be adjusted to reject particle strikes with the maximum energy level. As a result, at the device level, DAD-FF eliminates 99.999997% soft errors by heavy ions on a satellite orbiting at a height of 720 km, and shows greater reduction on SER (e.g. 1.3E10X in the best case) than the standard DFF (STD-FF) through TCAD and SPICE simulation. Moreover, a real chip was also fabricated in a CMOS 90nm technology and performed the experiment of radiation exposure in UCL, Belgium. The laboratory measurement indicates that at the system level, the radiation-hardened design by DAD-FFs achieves 15.69X and 2.62X improvements on the overall SER, compared with those by STD-FFs and DICEs, respectively.

This paper presents a fully digital binary-phase-shift keying (BPSK) demodulator for data and power telemetry. This demodulator recovers BPSK signals by detecting the symbol edge of the digitized received carrier. Parameters of the coupling coils, rectifier DC output, and data rate are taken into consideration in the early design stage. Given a limited coil size and quality factor, the demodulator achieves a data rate of 678kb/s with BER < 10-9 at a carrier frequency of 13.56MHz. Fabricated in a 0.18μm CMOS process, the chip area is 0.445mm square. The chip core dissipates 191μW at 13.56MHz. A system prototype was developed to transmit data and power simultaneously through a pair of coils.

With the recent evolution of medical device developments, physiological signal acquisition system is widely used in health monitoring, brain machine interface, and neural prosthesis, etc. In this paper, a multi-channel multi-mode biomedical signal acquisition and analysis platform is designed and implanted. The platform includes a customized low-distortion, high signal-to-noise ratio (SNR) analog to digital converter (ADC), and a field-programmable gate array (FPGA) with an embedded soft-core of 32-bit RISC processor. A multimode ADC was developed to meet the resolution and bandwidth requirement of different physiological signals. The soft-core and its corresponding software was designed and implemented to provide a versatile platform for different bio-medical applications. The integration of multi-mode data converter and signal processing platform enable the turnkey solution to develop different bio-medical applications such as on-line seizure detection, heart rate monitor, physiological signals recorder, etc.

the live demonstration shows the prototype of image recombination and processing system for one-dimensional multi-strip CMOS image sensors (CISs.) The proposed final system is discussed in the main paper, which takes advantage of the satellites' linear moving property to control the exposure time of CIS and provides the real-time ability to generate 11,200 × N high-resolution image for satellites' remote sensing applications. The prototype, which contains four strip CISs, is implemented to verify functionality and capability of real-time image acquisition and combination. The implementation result shows the proposed system, which demands four times larger throughput than the prototype, is feasible in a chip.

Approximately 1% of people in the world have epilepsy and 25% of epilepsy patients cannot be treated sufficiently by any available therapy. An automatic seizure detection system can reduce the time taken to review the EEG data by the neurologist for epilepsy diagnosis. In this paper, various EEG features integrated with the linear or non-linear classifiers are evaluated for seizure detection. For the EEG features, approximate entropy (ApEn) combined with 1) EEG power spectra or 2) autoregressive model (AR) are compared. In addition, the principle component analysis (PCA) is also utilized for feature extraction. For the classifiers, two linear models, linear least square (LLS) and linear discriminant analysis (LDA), and two nonlinear models, backpropagation neural network (BPNN) and support vector machine with radial basis function kernel (RBFSVM) are compared. The EEG signals of three Long Evans rats with spontaneous absence seizures are used for leave-one-out cross-validation. Experimental results shows that combining ApEn and multi-band EEG power spectra are superior to the combination of ApEn and AR model for all classifiers. The best average accuracy is 97.5% performed by RBFSVM and the linear models can achieve to higher than 95%. The automatic seizure detection method can be utilized to drive the seizure warning device or seizure control devices in the future to enhance the patients' quality of life.

A wide-bandwidth low-power CT ΣΔ modulator with 10MHz signal bandwidth is implemented in TSMC 0.18 µm CMOS process in this paper. To realize such application scenario, the proposed modulator comprises a third-order active-RC loop filter and a 4-bit internal quantizer operating at 320 MHz clock frequency. To reduced clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the excess loop delay compensation is achieved by the discrete-time deviator structure. The simulation result achieves above 74-dB SNDR (12 ENOB) over a 10-MHz signal band. The power dissipation is 36mW from a 1.8-V supply and the energy per conversion is 235fJ from post-layout simulation. The proposed circuitry can be utilized in low-power medical imaging and modern wireless communications.

In this paper, a glitch-free DLL-based clock generator using a feedback-switching detector is proposed for a programmable power management system. The proposed circuitry utilizes feedback switching detectors to eliminate undesired glitch problem which is generated by switching feedback stage of a DLL. The clock generator can generate clock signals ranging from 100MHz to 1.6GHz. The peak to peak jitter is 23.168ps and power consumption is 37.8mW at 1.6GHz. The proposed clock generator is implemented in TSMC 0.18µm process and occupies only 0.039 mm2which is suitable for the power management systems.

A 1.08-Gb/s CMOS half-rate burst-mode clock and data recovery (BMCDR) circuit with a novel jitter reduction technique is presented. There are several discrete delay time values in the programmable delay circuit (PDC) of the edge detector can be selected by five addressing inputs to create a "dynamic average" delay time that equals to half-of-data period (Tbit/2) to ensure minimum jitter accumulation. A prototype chip was designed with TSMC 0.18-mum CMOS 1P6M technology. The occupied die area of the CDR is 0.99 times 0.97 mm2, and the power consumption is 36 mW under a 1.8-V supply voltage.

A low-cost and high linear voltage reference circuitry is designed and implemented in TSMC 0.18 mum CMOS technology. Previous research has proposed the use of MOS transistors operated in the weak inversion region to replace the bipolar devices with conventional PTAT (proportional to absolute temperature) circuits. However, such solutions often cause linearity problem in high temperature region because of the current leaking devices in modern deep sub micron and nano-scale CMOS technology. The proposed circuit utilized temperature complementation technique on two voltage references, PTAT and IOAT (independent of absolute temperature) references, to enhance the linearity and produce a stable IOAT voltage reference. Based on the measurement results, the R-square of PTAT reference is better than 0.9 and the temperature coefficient of IOAT reference is 14 ppm/degC in a considerable wider temperature range from -60degC to 140degC. The occupied chip area is 0.00126 mm . Thus, a fully integrated temperature sensor with wider temperature range is designed and easily to integrate to modern system-on-chip designs with minimal efforts.