Space-based radar is a suite of applications that presents many unique system design challenges. In this paper, we investigate use of RapidIO, a new high-performance embedded systems interconnect, in addressing issues associated with the high network bandwidth requirements of real-time ground moving target indicator (GMTI), and synthetic aperture Radar (SAR) applications in satellite systems. Using validated simulation, we study several critical issues related to the RapidIO network and algorithms under study. The results show that RapidIO is a promising platform for space-based radar using emerging technology, providing network bandwidth to enable parallel computation previously unattainable in an embedded satellite system.

As NASA and other agencies continue to undertake ever challenging remote sensing missions, the ability of satellites and space probes to diagnose and autonomously recover from faults will be paramount. In addition, a more pronounced use of radiation-susceptible components in order to reduce cost makes the challenge of ensuring system dependability even more difficult. To meet these and other needs, a processing platform for space is currently under development at Honeywell Inc. and the University of Florida for an upcoming NASA New Millennium Program mission. Among other features, the platform deploys an autonomic software management system to increase system dependability. In addition, a mission manager has been investigated and developed to provide an autonomous means to adapt to environmental conditions and system failures. This paper provides a detailed analysis of the management system philosophy with a focus on the adaptable mission manager. A case study is presented that highlights the dependability and performance improvement provided by the mission manager and autonomic health monitoring scheme

The demand for processing power has been ever increasing with the growth of high-performance computing (HPC) applications and so have the constraints restricting the solutions to such requirements. High-performance distributed and parallel computing and custom-built, hardware-based computing have attempted to address this problem with some success but at a substantial cost. Recently, systems augmented with Field-Programmable Gate Arrays (FPGAs) offering a fusion of traditional parallel and distributed machines with customizable and dynamically reconfigurable hardware have emerged as a cost-effective alternative to traditional systems. However, providing a robust runtime environment for such systems to which HPC users have become accustomed has been fraught with numerous challenges. Dynamic scheduling of large-scale HPC applications in such parallel reconfigurable computing (RC) environments is one such challenge and has not been sufficiently studied to our knowledge. In this paper, we simulatively analyze the performance of several common HPC scheduling heuristics that can be used by an automated job management service to schedule application tasks on a parallel RC system. We also present a performance prediction model which the scheduling heuristics employ to schedule several common HPC applications on a collection of typical FPGA processing platforms.

RapidIO is an emerging standard for switched interconnection of processors and boards in embedded systems. We use discrete-event simulation to evaluate and prototype RapidIO-based systems with respect to their performance in an environment targeted towards space-based radar applications. This application class makes an ideal test case for a RapidIO feasibility study due to high system throughput requirements and real-time processing constraints. Our results show that a baseline RapidIO system is well suited to space-based radar, providing significant improvements over typical bus-based architectures. Our results also show that extensions to the RapidIO protocol such as cut-through routing and transmitter-controlled flow-control would provide minimal performance improvements for the applications under study.

The combination of high-performance processing power and flexibility found in network processors (NPs) has made them a good solution for today's packet processing needs. Similarly, the emerging technology of reconfigurable computing (RC) has made advances in packet processing as well as other point-solution markets. Current NP designs offer configurable elements but generally do not use dynamic RC techniques for run-time reconfiguration. Incorporating RC into NP designs to enhance packet processing is a natural progression for both of these emerging technologies. This paper presents the simulation results of a novel design for a RC-enhanced NP based on the Intel IXP1200 NIC design philosophy. The enhanced NP's performance is compared to that of the baseline NP in terms of three normalized traffic patterns and a case-study traffic pattern based on a military application. The results demonstrate that the enhanced NP significantly outperforms the baseline NP design in terms of latency for prioritized traffic that is non-uniform.