Modern digital systems can be viewed as compositions of combinational and sequential blocks. In the article, we discuss a case when sequential blocks are represented using a model of Mealy finite-state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. This article proposes a novel design method which allows diminishing the number of look-up table (LUTs) and increasing the operating frequency of multilevel LUT-based Mealy FSMs. The method is based on simultaneous use of such methods of structural decomposition as the transformation of states into FSM outputs and twofold state encoding. The proposed method results in three-level logic circuits of Mealy FSMs with regular systems of interconnections. Each function for any level of logic is implemented using a single LUT. An example of FSM synthesis with the proposed method is given. The experiments with standard benchmarks were conducted. The results of experiments show that the proposed approach leads to decreasing LUT counts from 11.9% to 62.6%. Also, it leads to increasing the operating frequency from 11.77% to 18.43% on average compared with other investigated approaches (Auto and One-hot of Vivado, JEDI, and replacement of FSM inputs and encoding the collections of outputs). The economy in used LUTs and gain in operating frequency grow with the growth of the FSM complexity.

The design and implementation of an embedded system is often a complex and complicated process. Usually it takes significant amount of time. This process is even more complex in the case of a distributed embedded system. Thus, it is necessary to search for new design methods that will improve software implementation time and simplify the verification process. One of the approaches is to use the behaviour models. Specific model transformations allow carrying hardware synthesis and obtaining either generated code fragments or the entire implementation. Furthermore, currently there is lack of models supporting the description of distributed embedded systems that allow for automatic synthesis, starting from the model, through its decomposition, to implementation. In this paper, we propose a new model: Interpreted Petri Nets for Embedded Systems (IPNES) for describing the behaviour of an embedded system. The model allows describing both a single-module system and an entire distributed system that requires processes synchronization and data exchange. This model contains a number of different elements that are necessary for operating of any embedded system. It can be used in the subsequent stages of distributed embedded system synthesis process, i.e. decomposition and automatic code generation.

A method is proposed allowing implementing logic circuit of Moore FSM with embedded memory block of FPGA chips. The method is based on replacement some part of the set of logical conditions by additional variables. It results in diminishing for the number of LUTs in the multiplexer used for replacement of logical conditions. An example of proposed design methods application is given.

The proposed method is targeted on reduction of hardware amount in logic circuit of Moore finite-state machine implemented with programmable logic arrays (PLA). The method is based on using more than minimal amount of variables in codes of FSM internal states. The method includes two stages of state encoding. The second stage is connected with recoding of states inside each class of pseudoequivalent states.