Recent work has shown that monolithic integration of voltage regulators will be feasible in the near future, enabling reduced system cost and the potential for fine-grain voltage scaling (FGVS). More specifically, on-chip switched-capacitor regulators appear to offer an attractive trade-off in terms of integration complexity, power density, power efficiency, and response time. In this paper, we use architecture-level modeling to explore a new dynamic voltage/frequency scaling controller called the fine-grain synchronization controller (FG-SYNC+). FG-SYNC+ enables improved performance and energy efficiency at similar average power for multithreaded applications with activity imbalance. We then use circuit-level modeling to explore various approaches to organizing on-chip voltage regulation, including a new approach called reconfigurable power distribution networks (RPDNs). RPDNs allow one regulator to "borrow" energy storage from regulators associated with underutilized cores resulting in improved area/power efficiency and faster response times. We evaluate FG-SYNC+ and RPDN using a vertically integrated research methodology, and our results demonstrate a 10-50% performance and 10-70% energy-efficiency improvement on the majority of the applications studied compared to no FGVS, yet RPDN uses 40% less area compared to a more traditional per-core regulation scheme.

In this paper we present a simple methodology that utilizes the timing-bins in a globally synchronized wireless sensor network to broadcast event information throughout the network. The proposed scheme enables classification as well as per node localization of an event by using bins as hop-counts. A simple implementation of immediate neighborhood validation is also proposed to prevent false-trigger. The neighborhood validation scheme enables self-healing of a faulty sensor node and can be disabled by incorporating self-validation. The proposed schemes are designed to be used in combination with impulse based UWB systems, and help reduce the need for complex MAC/Routing based packet communication in these networks. The proposed scheme implements dynamic duty-cycling as well as dynamic message sizing, ensuring low power consumption during idle as well as event communication phases. A further extension of this methodology can also be used for normal peer-peer packet based communication in conjunction with the event classification feature.

Impulse Radios within communication networks using Pulse Coupled Oscillator (PCO) global synchronization can be efficiently duty cycled for significant power savings. In this paper we utilize the emergent dynamical behavior in the PCO network to enable a simple event communication scheme particular to this type of network. In this scheme, each coupled radio node accesses the channel by simply changing its pulse repetition frequency in response to an event sensed by its sensor. This forces the network to a new, higher operating frequency, which can be locally measured at every node in the network to communicate occurrence of an event in the network. In this paper we show how this synchronization occurs and how it is ideally suited for low power operation. The proposed event propagation scheme enables a node to broadcast information about an event to an entire network in a simple fashion without the need of any data-packet formation or complex MAC/Routing protocols. We show that resynchronization and recovery of the network happens almost immediately. The latency involved corresponds to the distance-delay (due to finite speed of light) plus a very small circuit delay of (4-5ns) per hop related to detection of impulses.

In this paper we present the design and the measured results for a FCC-compliant UWB impulse transmitter (Tx) designed to operate in the 3-5GHz range. The transmitter uses a fast start-up, duty-cycled, current-starved ring-oscillator topology. A triangular pulse-shaping technique is utilized for spectrum-shaping to facilitate FCC compliance. The designed transmitter can be controlled to operate in 3-different bands centered at 3.5GHz, 4.0GHz, and 4.5GHz, with good inter-band isolation. The chip was fabricated in a 90nm CMOS technology, and was measured to consume only 2.8µW of leakage power and 2.9µW at 100Kbps of dynamic power. The data-rate can be scaled up to 5Mbps at 29pJ/pulse, while still staying compliant with FCC-mask even with non-random pulsing. The output voltage swing was measured to be ~450-500mV across a 50& load. The total power consumption of ~6µW at 100Kbps is an order of magnitude better than that of state-of-the-art designs, i.e. ~100µW, operating at same pulse rate.