Kian Jafari

dblp:21/9185 · DBLP profile ↗
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3ranked-venue papers
0as first author
3since 2021 · last 2026
0000-0003-4762-1536ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021
YearPublicationVenuePosition
2026 High-Speed Optical Binary Neural Network Accelerator Enabled by Nonvolatile MEMS Phase Shifters for Edge AI Applications
abstract
This paper presents a novel approach for implementing Binary Neural Networks (BNNs) utilizing nonvolatile optical phase shifters. These phase shifters employ a micro-electromechanical system (MEMS) tuning mechanism, which enables the adjustment of the refractive index and phase of the propagating mode. In this approach, the weights of the BNN can be controlled by applying electrical signals to the phase shifters. Moreover, due to the nonvolatile operation of these devices, the network’s weights remain stable even when the electrical power source is cut off. The phases of the propagating modes, manipulated by the proposed phase shifters, determine the logic of the photonic circuit. The in-memory design of this device eliminates the need for network register banks, thereby significantly reducing resource usage, footprint, and power consumption. This approach offers much faster operation than other technologies, such as CMOS or spintronics, making it particularly appealing for edge artificial intelligence applications.
Yashar Gholami, Behnam Saghirzadeh Darki, Kian Jafari, Mohammad Hossein Moaiyeri
IEEE Trans. Circuits Syst. I Regul. Pap.3
2025 Synergizing spintronics and quaternary logic: a hardware accelerator for neural networks with optimized quantization algorithm
Motahareh BahmanAbadi, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
J. Supercomput.4
2021 High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register
abstract
Multiple-valued logic (MVL) shows considerable advantages over binary logic in certain applications because of the increased informational content of its signals, and hence reduction in interconnects. Flip-flops (FFs) are the basic elements of many systems and are widely used in microprocessors due to their high performance. This article presents two spintronic ternary retention FFs, and a nonvolatile universal ternary shift register (NUTSR) based on gate-all-around carbon nanotube field-effect transistors (GAA-CNTFETs) and nonvolatile magnetic tunnel junction (MTJ). In the proposed input-aware ternary retention FF circuit, power consumption is significantly reduced by adding a magnitude comparator (MC) circuit and preventing duplicate data transfer to MTJs. Simulation results indicate that our design offers at least 22%, 40%, and 15% reductions in power consumption, backup time, and restore energy, respectively. Moreover, it eliminates the risk of data loss in the event of a sudden power outage.
Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri
IEEE Trans. Very Large Scale Integr. Syst.2