In this article, the design strategy with the analysis in the graph domain and changing the signal flow graph (SFG) of an amplifier are employed according to the graph rules at the system level. A three-stage amplifier, which expands the dual-path structure and buffering-based pole relocation amplifier through the graph domain inspection by using the graph rules, is proposed. By adding order of denominator in main fraction of the equivalent impedance of active zero block, the proposed amplifier can effectively increase the driving ability while enhancing the amplifier’s stability for a large range of capacitive load. The second pole is located at a higher frequency to increase the phase margin (PM). Circuit implementation of the proposed amplifier is simulated in 0.18-$\mu $CMOS standard technology with 0.004-mm2 active area and 8.8-$\mu $power consumption. Post-layout simulation results show 130 dB in dc gain, with a 670-kHz unity-gain frequency, while the amplifier uses a 400-fF compensation capacitor. The amplifier has obtained a PM of 60.4° at C$_{\text {L}} =3.7$nF. An average slew rate (SR) of 0.38 v/$\mu $s was measured when the proposed amplifier was in unity-gain configuration to drive a 3.7-nF load capacitor. FoMS and FoML in the proposed amplifier are improved by 116% and 107%, respectively.

Muller C-element (MCE) can be utilized in synchronous circuits by forming an oscillator so-called self-timed ring oscillators (STROs). STROs can oscillate in evenly spaced and burst modes, among which the former is desirable for synchronous design. This work introduces a new current mode logic (CML) MCE with an emphasis on evenly spaced oscillation mode in STROs. The proposed MCE is evaluated theoretically in terms of speed with load capacitances of$C_{L}=25$and 100 fF. The simulation result is in good agreement with analytical calculations, with an error of about 11%. Moreover, the speed, power, area, and Charlie and drafting effects of the proposed design are compared with those of other CML MCEs. The results show a better drafting effect (about 68% improvement) for the proposed design, leading to the evenly spaced oscillation mode in STROs. All simulations are implemented in 180-nm CMOS technology.

In this article, we proposed a new design called complementary fold-interleaved multiple-tail current mode logic (CFIMTCML) to implement logical functions with a fan-in higher than 2. This idea is implemented by alternately executing two steps. In the first step, a tail current is divided into multiple currents, but with a shallower depth from the ground to the common-mode point. It is applied on all fully stacked stages. The second step is implemented by alternating nMOS and pMOS differential pairs and utilizing current mirrors in adjacent logic levels. The proposed approach allows a minimum power supply equal to the conventional MCML inverter. Analytical details and design procedures are presented. The method has been validated with post-layout simulations considering 180 nm CMOS technology and supply voltage as low as 0.6 V. In particular, the SOP_X4 is implemented with the conventional SCL, MTCML, multifolded MOS current mode logic (MFMCML), and CFIMTCML. Results show that the proposed logic demonstrates 90%, 20%, and 50% power delay product (PDP) reduction than conventional SCL, MTCML, and MFMCML, respectively. Also, the results of implementation and comparison of other gates, such as the carry generator and 8-bit carry generator demonstrate, at least about 20% reduction of PDP. The delay increase rate at lower voltages for the proposed gates is slower than the counterparts (15 ps at 1.8 V to 124 ps at 0.6 V for the proposed and 27 ps at 1.8 V to 253 ps at 0.6 V for MFMCML). This mitigated degradation is a benefit of the proposed logic for low-noise/low-power applications demanding ultralow voltages.

The growing number of smart connected devices raises challenges in system reliability. Prediction of failures in Internet of Things (IoT) ecosystems is a significant problem, especially in smart healthcare or financial transfers. In this work, a novel framework and a cost-efficient (power consumption and area) aging tag for the remaining useful life estimation of IoT devices are introduced. Utilizing the proposed comprehensive system prevents failures in large IoT ecosystems. We chose the threshold voltage, a fundamental parameter of transistors as the aging criterion. Also, we considered process, supply voltage, and temperature (PVT) effects on the threshold voltage in the creation or selection of the proper comparison profile. The proposed framework is implemented in three distinct types of cloud machine learning (ML), edge ML, and a combination of proportion estimation and Zscore. Choosing between these three types is a tradeoff between accuracy and minimum resources requirement. A sample tag is fabricated and simulation and fabrication results verified the performance of the proposed system. The cloud ML framework estimated the remaining useful life of various test scenarios with less than 1% error. This means the system estimates the remaining lifetime for the next ten years with two weeks error. Furthermore, the implementation of optimized anomaly detection methods eliminates probable errors of measurement, storage, and data transmission.

In the Mesochronous Pipeline (MP), the clock period is the maximal of differences between the maximum/minimum delays of all stages. This value is less than the maximum delay between the memory elements, so MP is operating faster than the conventional pipeline (CP). To take full advantages of MP, in this paper, Automated Mesochronous Pipeline Scheduler (AMPS) for high performance digital circuits, is proposed which provides all allowed partitioning options generated by register allocation procedures obtained with varying maximum delay differences of stages. This allows a designer to select from design space produced by AMPS based on the desired specification. Unlike the traditional MP, AMPS utilizes automated scripts to extract the timing characteristics of the synchronizers and gates. This enables a designer to explore trade-offs between latency, power, and frequency. To evaluate our toolset, an 8-bit Carry Increment Adder (CIA), a 4-bit Binary-Coded Decimal (BCD) adder, a 4-bit ALU, and a set of circuits from ISCAS85 and ISCAS89 benchmarks are considered. All circuit level simulations are performed in the 65nm CMOS standard technology node. AMPS improves the frequency for its best solutions about 127.94% (on average) in comparison to the conventional pipeline scheme.

This article presents two novel structures for designing current mode logic (CML) digital circuits [MOS CML (MCML) and multiple tail CML (MTCML)] in ultralow-power (ULP) and high-speed (HS) applications. The transistor's bulk can be used as a digital signal input at a level, where it does not cause a disturbance to the operation of the transistor. Therefore, the number of transistors used in novel structures is reduced and it is possible to improve power delay product (PDP) and time propagation delay (TPD) in some of the tail currents. This technique is obtained through integrating the bulk-driven technique into the CML digital circuits, which are in the form of bulk-driven MCML (BD-MCML) and BD-MTCML. In the conventional CMOS technology, the proposed structures depend on the type of substrate. The BD-MCML structure uses a deep n-well technology and the BD-MTCML uses an n-well technology. The CML gates, such as AND, XOR, and D-latch, are suggested. The systematic use of the proposed structures is discussed in both HS and ULP applications. Finally, an unsigned multiplier is designed in the form of the BD-MTCML with a conventional 180-nm technology. Mixed-signal circuits are Serial/De-serial (SerDes), optical receivers, radio frequency (RF) receivers, and line drivers on the HS approach, and also video processors and A/D and D/A converters on the ULP approach.

The large size and complexity of the modern digital hardware impose great challenges to design and validation. Hardware Description Languages (HDLs) and System-Level Description Languages (SLDLs) rely on sequential discrete event semantics. Parallel Discrete Event Simulation (PDES) has recently gained extensive attention for parallelizing these languages due to the ever-increasing complexity of embedded and cyber physical systems. However, PDES application has not yet reached acceptable maturity and pervasiveness for accelerating computer architecture problems. This is due to inherent complexity of hardware components that require using different advanced PDES techniques. In this paper, we look at the main problem from a radically different angle. First, we suppose there is only a single universal discrete event model of computation for simulation purely defined by distributed optimistic PDES, i.e., logical-process-based event scheduling worldview. Second, we construct a new parallel system-level simulation language called OSML for ESL. Third, we propose a unified Cloud-based CAD tool called Troodon to automatically parallelize existing hardware languages atop OSML. To the best of our knowledge, OSML is the first work on optimistic synchronization applied to hardware-specific SLDLs and hardware models at different levels of abstraction in ESL, which contain complex data structures by proposing a hybrid checkpointing scheme.

The Internet of Things (IoT) devices are manufactured under different fabrication quality standards, considering the wide variety of vendors. As a result, global process variations in the IoT system-on-chip (SoC) are an enormous concern that can affect reliability of the device. Among the components in a typical SoC, oscillator is the most susceptible element to process variations. This paper proposes a feedback-assisted digitally controlled oscillator (DCO). The DCO has 512 operating modes, for wide-range frequency tuning from 0.6 to 3.1 GHz. By adding a dynamic feedback to inner current-controlled oscillator using a frequency-to-current converter, the DCO remains linear and invariant to the process for entire 2.5-GHz frequency band. Thanks to pseudodifferential cross-coupled structure used in each stage, this paper achieves a 2.3 ps deterministic jitter at 1.87-GHz output frequency. Furthermore, Monte Carlo analysis is performed at 1.87-GHz frequency; indicate that standard deviation from the mean is 2.47% that verifies reliability of this design. Power consumption varies from 0.86 to 3.68 mW at 1.2 V supply voltage, corresponding to the code word. The DCO is implemented in 65-nm standard CMOS process.

Abstract Transport Layer Security (TLS) is the most popular security protocol of the transport layer. It is widely used to provide basic security services of authentication, confidentiality, and integrity of sensitive data. It is carried out in critical untrusted networks between client and server entities, such as e‐commerce and online transactions. Despite multiple capabilities, TLS protocol is vulnerable to the malicious server attacks that may cause a serious threat to TLS‐based e‐commerce communications. This should be considered as the first problem of this protocol. The other problem of TLS is sending many messages during the handshake phase for providing a successful negotiation and a secure communication. So, this phase is the most complex and time‐consuming phase of the TLS protocol. This causes decreasing of service capacity and using more time. We are going to propose a new protocol based on trust model called “TSSL protocol” in this paper. This model is used to conquer the disadvantages with security of the TLS protocol. Through this paper, it is going to be indicated that the proposed model has higher levels in both security and performance compared with the conventional TLS. Copyright © 2014 John Wiley & Sons, Ltd.

ABSTRACT Recently, there has been a spate of interest in Internet voting systems because of advantages such as participation, efficiency, accuracy, and transparency. However, challenges for having a secure i‐voting system are considerable. Unless these systems are designed and implemented carefully, citizens might lose their trust on the whole voting process. This paper introduces a novel online voting protocol, which satisfies the desired security requirements of i‐voting as collusion resistance, fairness, coercion\bribery, and secure voting platform. Although Internet voting systems provide convenience for voters by requiring just a PC and an Internet connection, they might be subject to some drawbacks as PCs are very susceptible to malware and sophisticated attacks. To clarify, voter side insecure platform is one of the biggest challenges in Internet voting, which would breach voter's privacy and also affect the integrity of election. In this paper, we present an alternative to the voters' insecure PCs. Java Card 3 is the latest version of Java Card, which could be considered as voter's portable secure Web server. It can obtain an IP address and communicate with other network nodes with hypertext transfer protocol secure (HTTPS). Therefore, regardless of utilizing a trusted device at the client side, end‐to‐end security is guaranteed. This means that Java Card 3 can resolve challenges, which are posed by insecurity of the vote casting PC. Furthermore, to enhance the security and guarantee the confidentiality and integrity of the data, which are stored in the card during the voting process, we have used Java information flow. An implementation of this protocol is proposed on the basis of Java Card 3 servlet container and Web server technology in which the card and electoral servers communicate on a machine‐to‐machine basis. Copyright © 2014 John Wiley & Sons, Ltd.