Precise estimation of correlation or similarity between two random variables lies at the heart of signal detection, target localization and pattern recognition. In this paper, we show that there exists a large class of multiplier-less analog correlators that can demonstrate a higher signal-to-noise ratio (SNR) compared to a conventional multiply-accumulate (MAC) based correlator. The multiplier-less design uses a Margin Propagation (MP) principle combining rectifying diodes in a symmetric circuit architecture. Using Price’s theorem we present a novel analytical framework that can be used to understand the steady-state behavioral response of different MP correlator circuits. The analytical results have been verified using transient and steady-state circuit simulations of correlator circuits designed in a standard CMOS process.

The relentless demand for data in our society has driven the continuous evolution of wireless technologies to enhance network capacity. While current deployments of 5G have made strides in this direction using massive multiple-input-multiple-output (MIMO) and millimeter-wave (mmWave) bands, all existing wireless systems operate in a half-duplex (HD) mode. Full-duplex (FD) wireless communication, on the other hand, enables simultaneous transmission and reception (STAR) of signals at the same frequency, offering advantages such as enhanced spectrum efficiency, improved data rates, and reduced latency. This article presents a comprehensive review of FD wireless systems, with a focus on hardware design, implementation, cross-layered considerations, and applications. The major bottleneck in achieving FD communication is the presence of self-interference (SI) signals from the transmitter (TX) to the receiver, and achieving SI cancellation (SIC) with real-time adaption is critical for FD deployment. The review starts by establishing a system-level understanding of FD wireless systems, followed by a review of the architectures of antenna interfaces and integrated RF and baseband (BB) SI cancellers, which show promise in enabling low-cost, small-form-factor, portable FD systems. We then discuss digital cancellation techniques, including digital signal processing (DSP)- and learning-based algorithms. The challenges presented by FD phased-array and MIMO systems are discussed, followed by system-level aspects, including optimization algorithms, opportunities in the higher layers of the networking protocol stack, and testbed integration. Finally, the relevance of FD systems in applications such as next-generation (xG) wireless, mmWave repeaters, radars, and noncommunication domains is highlighted. Overall, this comprehensive review provides valuable insights into the design, implementation, and applications of FD wireless systems while opening up new directions for future research.

$N$-path switched-$RC$circuits have been extensively investigated as a promising solution for realizing various novel functionalities, including on-chip tunable high-$Q$filters, true time delays operating beyond the delay-bandwidth product, and non-reciprocal components. The clock frequency typically sets important parameters of the functionality, such as the frequency of the filter, the amount of achievable delay etc. The ability to tune the clock frequency through a wideband synthesizer enhances the reconfigurability of$N$-path switched-$RC$circuits, but the presence of multiple independent$N$-path circuits on a chip results in the need for multiple independent wideband synthesizers. Here, we introduce a novel concept of rotary clocking in$N$-path circuits which enables us to passively frequency shift any$N$-path filter by either rotating clockwise or anti-clockwise the clocks exciting the switches of each of the paths. The effect of rotary clocking is analyzed using linear periodically-time-variant (LPTV) circuit theory, and has been verified through simulations and measurements. The effects of quantization due to finite clock phases, and the resultant spurs produced by this method, are also analyzed and compared with measurement results. Measurement results are presented for a two-port$N$-path filter implemented in a 65-nm CMOS 0.1-1 GHz highly-reconfigurable self-interference canceling receiver. The two-port filter achieves a maximum frequency shift of$f_{s}/8$in the steps of$f_{s}/160$and also has a phase control covering all of 360° in steps of 45°.

N-path commutated capacitive networks provide a practical solution to implement highly sought on-chip high-Q filtering applications in which the use of lumped inductors is undesirable due to their significant footprints and low Q-factors. Recently, it has been also revealed that N-path networks can also exhibit other interesting functionalities, such as nonreciprocal phase-shifting and ultra-wideband true time delay, providing a path to miniaturization of various reciprocal and nonreciprocal devices. The analytical treatment of these networks, however, remains challenging, because their operation involves frequency mixing produced by the time modulation. In this article, we present a highly accurate frequency-domain approach for the analysis of N-path networks based on perturbation theory. Our method compares favorably to the state-of-the-art polyphase analysis by being much simpler mathematically, yet providing results essentially indistinguishable from numerical simulations, while offering physical insights into the N-path filter operation. We particularize the solution for the high-Q operation regime and obtain simple closed-form analytical expressions for harmonic transfer functions, scattering parameters and baseband impedance.