Spike-Timing-Dependent Plasticity (STDP) is a biologically inspired mathematical rule in which the timing difference between pre-synaptic and post-synaptic spikes dictates changes in synaptic strength. Due to its biological plausibility, STDP is widely employed in Spiking Neural Networks as a key training mechanism, facilitating efficient brain-like learning in neuromorphic systems. Two common variants, pair-based STDP and triplet-based STDP, are suited for diverse neural computing scenarios. However, improper use of these variants may degrade network performance or lead to undesired outcomes. In this paper, we propose a flexible hybrid STDP hardware implementation that supports two STDP learning rules and two computational schemes within a unified framework. We demonstrate its application by mapping the computational schemes to the MNIST classification task. The proposed architecture is validated on a Xilinx XA Spartan-7 FPGA. Compared to state-of-the-art approaches, our architecture improves power efficiency with a 21.5% reduction in resource consumption.