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Gabriel Gallin

dblp:210/2670 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2019
0000-0002-9644-9704ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 44% Integrated circuit design · 44% Electronic design automation · 13%
Network and information security
1 paper
Cryptographic primitives and cryptanalysis · 100%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › FPGA-based hardware security
FPGA-based cryptography
0.412019
Generation of Finely-Pipelined GF(PP) Multipliers for Flexible Curve Based Cryptography on FPGAs · IEEE Trans. Computers 2019
Integrated circuit design › digital circuit design › arithmetic circuit design
modular multiplier
0.412019
Generation of Finely-Pipelined GF(PP) Multipliers for Flexible Curve Based Cryptography on FPGAs · IEEE Trans. Computers 2019
Cryptographic primitives and cryptanalysis › public-key cryptography
elliptic curve cryptography
0.112019
Generation of Finely-Pipelined GF(PP) Multipliers for Flexible Curve Based Cryptography on FPGAs · IEEE Trans. Computers 2019
Cryptographic primitives and cryptanalysis › public-key cryptography › elliptic curve cryptography
hyperelliptic curve cryptography
0.112019
Generation of Finely-Pipelined GF(PP) Multipliers for Flexible Curve Based Cryptography on FPGAs · IEEE Trans. Computers 2019
Electronic design automation › high-level synthesis
VHDL generation
0.112019
Generation of Finely-Pipelined GF(PP) Multipliers for Flexible Curve Based Cryptography on FPGAs · IEEE Trans. Computers 2019

Methods — techniques the papers use, named apart from their topics

fine-grained pipelining · 0.8DSP slice mapping · 0.8
YearPublicationVenuePosition
2019 Generation of Finely-Pipelined GF(PP) Multipliers for Flexible Curve Based Cryptography on FPGAs
abstract
In this paper, we present modular multipliers for hardware implementations of (hyper)-elliptic curve cryptography on FPGAs. The prime modulus P is generic and can be configured at run-time to provide flexible circuits. A finely-pipelined architecture is proposed for overlapping the partial products and reductions steps in the pipeline of hardwired DSP slices. For instance, 2, 3, or 4 independent multiplications can share the hardware resources at the same time to overlap internal latencies. We designed a tool, distributed as open source, for generating VHDL codes with various parameters: width of operands, number of logical multipliers per physical one, speed or area optimization, possible use of BRAMs, target FPGA. Our modular multipliers lead to, at least, 2 times faster as well as 2 times smaller circuits than state of the art operators.
Gabriel Gallin, Arnaud Tisserand
IEEE Trans. Computers1