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Zhaorui Chen

dblp:210/2973 · DBLP profile ↗
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4ranked-venue papers
3as first author
2since 2021 · last 2026
0009-0000-1704-2766ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021Applied, interdisciplinary, general and emerging computing · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 1 · 1 since 2021Human-computer interaction and ubiquitous computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Reconfigurable computing and FPGAs · 50% Hardware accelerators and domain-specific architectures · 43% High-performance computing · 7%
Artificial intelligence
1 paper
Efficient and distributed learning · 77% Deep learning architectures and training · 23%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
coarse-grained reconfigurable architecture
1.012026
Data Transfer Optimization for Loop Mapping on CGRAs via Polyhedral Transformation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Reconfigurable computing and FPGAs › coarse-grained reconfigurable architecture
loop mapping
1.012026
Data Transfer Optimization for Loop Mapping on CGRAs via Polyhedral Transformation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Machine learning › Efficient and distributed learning
model compression
0.912025
DynaX: Sparse Attention Acceleration with Dynamic X: M Fine-Grained Structured Pruning · ASPLOS (2) 2025
Machine learning › Efficient and distributed learning › model compression › pruning
structured pruning
0.912025
DynaX: Sparse Attention Acceleration with Dynamic X: M Fine-Grained Structured Pruning · ASPLOS (2) 2025
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.912025
DynaX: Sparse Attention Acceleration with Dynamic X: M Fine-Grained Structured Pruning · ASPLOS (2) 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
sparse attention accelerator
0.912025
DynaX: Sparse Attention Acceleration with Dynamic X: M Fine-Grained Structured Pruning · ASPLOS (2) 2025
High-performance computing › data transfer
data transfer optimization
0.312026
Data Transfer Optimization for Loop Mapping on CGRAs via Polyhedral Transformation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Machine learning › Deep learning architectures and training
attention mechanism
0.312025
DynaX: Sparse Attention Acceleration with Dynamic X: M Fine-Grained Structured Pruning · ASPLOS (2) 2025
Machine learning › Deep learning architectures and training › attention mechanism
sparse attention
0.312025
DynaX: Sparse Attention Acceleration with Dynamic X: M Fine-Grained Structured Pruning · ASPLOS (2) 2025

Methods — techniques the papers use, named apart from their topics

dynamic pruning · 1.7polyhedral transformation · 1.0loop pipelining · 1.0
YearPublicationVenuePosition
2026 Data Transfer Optimization for Loop Mapping on CGRAs via Polyhedral Transformation
abstract
Coarse-Grained Reconfigurable Arrays (CGRAs) play an important role in accelerating computation-intensive applications due to their flexibility and power efficiency. Most existing mapping works for CGRA assume that all the data of a loop kernel can be previously moved from DRAM to ScratchPad Memory (SPM) with one data transfer. However, when targeting low-power CGRAs, the SPM can hardly hold the entire data even for a small loop kernel, and it inevitably incurs multiple data transfers, leading to notable costs. In this case, where and how to perform data transfer considering the DRAM access behavior is crucial to the overall execution performance. To this end, this paper proposes a data transfer optimization method to simultaneously optimize loop pipelining and data transfer. Since there is an interplay between loop structure and data transfer, we establish an optimization problem considering both polyhedral transformation and transfer strategy exploration, offering opportunities to find the near-optimal data transfer strategy within the search space. The experimental results show that compared with existing methods, our method can achieve 1.36×–4.55× speedup for loop kernels with different on-chip buffer sizes, and only increase the compilation time by a small amount.
Zhaorui Chen, Liao Huang, Xiao Xiong, Dajiang Liu
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2025 DynaX: Sparse Attention Acceleration with Dynamic X: M Fine-Grained Structured Pruning
Xiao Xiong, Zhaorui Chen, Yue Liang 0004, Minghao Tian, Jiaxing Shang, Dajiang Liu
ASPLOS (2)2
2020 CSCLRec: Personalized Recommendation of Forum Posts to Support Socio-collaborative Learning
Zhaorui Chen, Carrie Demmans Epp
EDM1
2017 Multimodal interaction in augmented reality
abstract
With the boost of computing power in mobile devices and availability of cloud APIs in recent years, mobile augmented reality (AR) applications have become increasingly embedded in people's everyday life. However, effective and intuitive interaction between virtual and real worlds in these AR applications is still an open question. In this paper, we make one step towards an answer by exploring the possibility of incorporating two input modalities, gesture and speech, for enhancing user experience in AR applications.
Zhaorui Chen, Jinzhu Li, Yifan Hua, Rui Shen 0002, Anup Basu
SMC1