Abstract The Fieldbus approach in today’s automation networks represents a significant step toward decentralization, enabling data preprocessing within field devices. Combined with real-time microcontroller response, this capability improves the control process and reduces the computational load on centralized automation controllers. This enables easy remote configuration of devices that require advanced device communication beyond standard data exchange. Reading and updating data from Modbus devices involves the use of polling, a technique that repeatedly scans the registers of each device. The scientific and practical contributions realized in the field of industrial communication on distributed systems are given by highlighting the scenarios in which Modbus devices are integrated and transactions on the communication bus for reading a fixed number of registers located at consecutive addresses, and the improvement enabled by the Modbus Extension (ModbusE) protocol. Based on the proposed mathematical model, with the equations customized for the current scenario, the practical results show the update times of the values on a device that has a maximum number of 50 addresses of the holding register and that are located at consecutive addresses. The results obtained by the authors of this article are presented through the analysis of Modbus transmission and the advantages proposed by ModbusE.

Actual trends in the real-time system field consists of migration towards complex central processing unit (CPU) architectures with enhanced execution predictability and rapid CPU contexts switch, thus obtaining high-performant control systems. The main objective of this paper is to present the results obtained following the implementation of real-time operating systems (RTOS) functions in hardware. Based on the CPU resource multiplication concept, actual researches has been focused on synthesizing in field-programmable gate array (FPGA) and implementing innovative solutions to improve RTOS performance. The results are materialized by validating an efficient hardware scheduler micro-architecture, from which a remarkable efficiency and a plus of performance and predictability are obtained. The experimental results, the FPGA resource requirements for implementation of the processor in different configurations, and the comparisons with other similar processor architectures are presented in order to verify theoretical aspects proposed through this paper.