In addition to the conventional ADC design tradeoffs between power, speed, and accuracy, radiation tolerance is the fourth factor for ADCs used in radiation environments. This paper describes radiation-tolerant (RT) ADC design tradeoffs and design strategies. Then, the paper introduces a 13-bit RT pipelined-successive-approximation register (pipelined-SAR) ADC fabricated in 65 nm CMOS technology based on the concluded tradeoffs. To further improve the ADC power efficiency, a semi-time-interleaved (Semi-TI) structure is employed. Besides, the ping-pong auto-zeroing (AZ) scheme is implemented in the residue amplifier (RA) to reduce the TID-induced offset while maintaining low power dissipation. The proposed ADC is designed and hardened against Single Event Effects (SEEs) and Total Ionizing Dose (TID) effects from the structure to layout levels. All sub-blocks were examined, and only the critical blocks were hardened to avoid over-hardening. From the measurement results, the prototype ADC attains an 80 MS/s sampling rate and achieves 70.8-dB SNDR and 80.3-dB SFDR at the Nyquist input frequency. With a total power consumption of 13.8 mW, the prototype ADC establishes a state-of-the-art Walden Figure of Merit of 60.7 fJ/conv step, yielding an efficiency comparable to non-RT ADCs with similar specifications. Irradiation tests validate the consistent performance of the ADC up to a cumulative dose of 500 krad (Si) in X-ray testing, while laser testing indicates a robust SEE threshold and swift post-SEE recovery.

This paper addresses decision-making challenges in mixed traffic environments comprising both conventional human-operated vehicles (HVs) and connected automated vehicles (CAVs). Our proposed framework is exemplified using a ramp merging scenario and is structured as an optimization problem, in which a merge sequencing problem and a trajectory planning problem are embedded and solved by a bi-level hybrid centralized-decentralized model predictive control (HMPC) approach. The HMPC framework we introduce leverages centralized edge computing for efficient merge decision optimization through a dynamic-programming approach and decentralized mobile computing for distributed trajectory planning through three different optimization algorithms. Simulation results show that compared to open-loop control, the proposed framework can ensure system efficient ramp-merging control, and exhibits robustness in the presence of uncertainty caused by the stochastic driving behaviors of HVs. In addition, it is found that mobile-edge hybrid framework can reduce the computational time to the millisecond-level, potentially meeting real-time computational requirements.

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.