The generalization ability of visual reinforcement learning, which allows the policy trained in the source domain to guide agents in similar unknown target environments, is one of the cores applied to visual navigation and autonomous driving. Recently, methods such as data augmentation techniques, self-supervised learning methods, and the generative adversarial network were employed to enhance the generalization capability of policy neural networks in visual reinforcement learning. However, current state-of-the-art methods, after utilizing domain-general latent features to train the RL policy, result in the loss of certain state-specific features, leading to diminished policy performance following generalization. To tackle these challenges, we designed a technical framework called self-expert imitation with purifying latent features, which enables the trained policy to effectively guide agents in scenarios similar to the training environment, without compromising the performance of the policy-guided agent in task completion. Additionally, a novel method was developed for separating domain-general and domain-specific latent vectors based on a variational autoencoder, enabling the domain-general component to exhibit strong and stable zero-shot generalization performance in unseen visually similar domains. Extensive experiments on the CarRacing game demonstrated that our approach achieves strong and stable generalization performance in unseen environments, without compromising the performance of the policy in guiding agents to complete tasks.

The exponential growth in data communication and increase in network size have led to various intrusions and attacks. An Intrusion Detection System (IDS) can be provided as a crucial component of a network or database to ensure the security of data communication over a network. The network size is large, a large dataset may comprise more irrelevant, redundant, and high-dimensional features that impact feature classification, thus affecting the intrusion detection rate. This study presents a new hybrid enhanced normalised Crow Search Algorithm (CSA) and Particle Swarm Optimisation (PSO) technique to address feature selection issues and to classify global best features using a random-forest classifier. In the proposed algorithm, the benefits of the CSA between the search strategy and rapid convergence phenomenon of the PSO algorithm are utilised to select the global best solution in a large search space. A random-forest classifier is used to classify the features after they are updated with weight values for significant features, assessing the asymptotic variance of features and points that are closest to the optimal solution. The asymptotic features are subjected to the weighted least mean square (WLS) method to eliminate large deviations among the features. The random-forest classifier distinguishes between normal records and abnormal intrusion records. The performance assessment of the proposed hybrid IDS model is performed by utilising two datasets, which reveals that the proposed model outperforms other existing models. The simulation outcomes show higher accuracy rate, precision value, recall factor, and F1-Score, revealing the efficacy of the IDS model.

As interconnects dominate circuit performance in modern field programmable gate arrays (FPGAs), placement becomes a crucial stage for timing closure. Traditional FPGA placers seldom consider the timing constraints and, thus, may lead to illegal routing solutions. In this article, we present an incremental timing-driven placement flow for advanced FPGAs. First, a timing-based global placement strategy is designed to guide heterogeneous blocks to desired locations with satisfied timing constraints. Then, a timing-aware packing algorithm is developed to mitigate the design complexity while improving the timing results. Finally, we propose a critical path-based optimization method to generate optimized layout without timing violations. We evaluate our algorithm based on industrial circuits using an advanced FPGA device. The experimental results show that our placer achieves a 5.1% improvement in worst slack and produce placements that require 16.7% less time to route when compared with the leading commercial tool Xilinx Vivado.

Modern FPGAs often contain heterogeneous architectures and clocking resources which must be considered to achieve desired solutions. As the design complexity keeps growing, placement has become critical for FPGA timing closure. In this paper, we present an analytical placement algorithm for heterogeneous FPGAs to optimize its worst slack and clock constraints simultaneously. First, a heterogeneity-aware and memory-friendly delay model is developed to accurately and rapidly assess each connection delay. Then, a two-stage clock region refinement method is presented to effectively resolve the clock and resource violations. Finally, we develop a novel timing-based co-optimization method to generate optimized placement without any clocking violations. Compared with the state-of-the-art placer based on the advanced commercial tool Xilinx Vivado 2019.1 with the Xilinx 7 Series FPGA architecture, our algorithm achieves the best worst slack and routed wirelength while satisfying all clock constraints.

As the feature sizes keep shrinking, interconnect delays have become a major limiting factor for FPGA timing closure. Traditional placement algorithms that address wirelength alone are no longer sufficient to close timing, especially for the large-scale heterogeneous FPGAs. In this paper, we resolve the crucial FPGA placement problem by optimizing wirelength and timing simultaneously. First, a smoothed routing-architecture-aware timing model is proposed to accurately estimate each interconnect delay. Then, a timing-driven delay look-up table is constructed to further speed up delay access. Finally, we present an effective wirelength and timing co-optimization strategy to produce high-quality placements without timing violations. Compared with Vivado 2019.1 on Xilinx benchmark suites for xc7k325t device, experimental results show that our algorithm achieves not only a 6.6% improvement in worst slack but also a 3.2% reduction for routed wirelength.

A SAR-ATR method with favorable performance on translational invariance is proposed in this paper. Nowadays, supervised learning is the main way to realize image processing and target detection, but performance of most trained models will be greatly influenced by distribution of targets in training samples. In some recent researches of SAR-ATR, models trained on MSTAR dataset apply methods of data augmentation to increase randomness of target position in training samples, so that the models could have a certain capability of translational invariance. The method that we proposed based on convolutional neural network (CNN) doesn't need operation of data augmentation at all, and the comparison experiments based on manually shifted target slices proved that our model performed better in detecting and recognizing shifted targets. Experiments show that the proposed method can accurately locate position of different kinds of shifted targets and realize detection and recognition correctly.

The target detection and recognition integration in large scene SAR images based on Region Proposal Regression (RPR) is proposed in this paper. In traditional three-stage process of SAR target recognition: detection-discrimination-classification/recognition, many factors between detection and recognition will greatly affect the result of recognition, such as the difference of target region size and target location between detection results and training samples. The proposed method which uses the structure of Deep Convolutional Neural Network (DCNN), can integrate the traditional three-stage process as a whole system at the base of detecting and recognizing targets at the same time. The experiments based on SAR simulation image data show that, the proposed method can accurately and directly recognize multi-class SAR targets in large scene images.