In mixed-criticality real-time systems, system resources must be sufficiently separated to guarantee non-interference of critical functions. This leads to fixed boundaries between critical and non-critical parts of a system impeding change, repair, or proactive means to improve reliability. With conventional methods, moving the boundaries at runtime to manage the resource usage without respecting essential isolation requirements in mixed-criticality systems increases the risk of failure and must, therefore, be avoided. In this paper, we present and evaluate a safe online reconfiguration approach for many-core platforms. It satisfies safety standards isolation requirements and supports continuous real-time system operation as required in many application domains. It is particularly suited to provide proactive actions in the face of foreseen system failures improving availability without increased risk of failure during reconfiguration. Experimental results on a realistic usecase indicate that the proposed approach allows predictable online reconfigurations with tolerable latency overhead.

While Networks-on-Chip (NoCs) are the prevalent solution to provide a scalable interconnect for the complex multiprocessing architectures, their associated energy consumptions have immensely increased. Specifically, hard real-time Networks-on-chip must manifest limited energy consumption as reliability issues in such a shared resource jeopardize the whole system safety. In this paper, we propose a safe and efficient approach that allows global and online energy management under temporal guarantees, i.e., all deadlines of critical functions are met. The approach introduces a control-layer to save energy on the NoC data layer through multiple Power-Aware Network Controllers (PANCs). We explore through PANCs the potential efficiency of integrating multiple energy-savings schemes in the face of the diversity of energy dissipation sources. To safely apply the PANCs in hard real-time systems while meeting the deadlines, a formal worst-case timing analysis of the additional latency induced by the control layer is provided. Experimental results demonstrate the diversity of NoC energy-savings under different combinations of energy-savings schemes. Also, the scalability of the approach is provided, inducing small area overhead.

This paper deals with challenges and possible solutions for incorporating self-awareness principles in EDA design flows for autonomous systems. We present a holistic approach that enables self-awareness across the software/hardware stack, from systems-on-chip to systems-of-systems (autonomous car) contexts. We use the Information Processing Factory (IPF) metaphor as an exemplar to show how self-awareness can be achieved across multiple abstraction levels, and discuss new research challenges. The IPF approach represents a paradigm shift in platform design by envisioning the move towards a consequent platform-centric design in which the combination of self-organizing learning and formal reactive methods guarantee the applicability of such cyber-physical systems in safety-critical and high-availability applications.

Networks-On-Chip (NoCs) designed to host advanced embedded applications require simultaneously high performance and efficient real-time guarantees under tight power limitations. Static power management is no longer sufficient to fulfill these goals in the context of a highly dynamic environment, e.g. autonomous driving, leading to mode-dependent system's behavior and substantial changes in traffic patterns. For this purpose, we propose a global and self-aware power management for NoCs. Dynamic voltage and frequency adjustments are performed at runtime depending on the number of currently active applications using protocol-based synchronization. The safety of a solution is assured by formal analysis and extensive experimental evaluation using an vehicle assistance functions, as well as synthetic benchmarks. The proposed scheme provides the desired performance, and when compared with the state-of-the-art approach, it significantly decreases power footprint of the NoC - up to 59% in the considered realistic use-case.